Concurrent error detection in arithmetic and logical operations using Berger codes

Lo, Jien-Chung; Thanawastien, Suchai; Rao, T.R.N.

doi:10.1109/arith.1989.72831

Cited by 25 publications

(9 citation statements)

References 8 publications

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“…In the field of IC security, widespread attention has been paid to the protection against fault injection attacks [5][6][7][8][9][10], resulting in multiple measures to prevent the ICs from being attacked by fault injection. The typical measures include physical protection [11], the hardware/time redundancy (module duplication/re-computation) method [12][13][14][15], and the error detection codes (EDC)-based technique [10,[16][17][18][19][20][21][22][23]. Among them, the EDC-based technique achieves the best tradeoff between fault coverage and hardware/time overheads [24].…”

Section: Introductionmentioning

confidence: 99%

A Secure Architecture for Modular Division over a Prime Field against Fault Injection Attacks

Qin

2020

Applied Sciences

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Fault injection attacks pose a serious threat to many cryptographic devices. The security of most cryptographic devices hinges on a key block called modular division (MD) over a prime field. Although a lot of research has been done to implement the MD over a prime field in hardware efficiently, studies on secure architecture against fault injection attack are very few. A few of the studies that focused on secure architecture against fault injection attack can only detect faults but not locate faults. In this regard, this paper designs a novel secure architecture for the MD over a prime field, which can not only detect faults, but also can locate the error processing element. In order to seek the best optimal performance, four word-oriented systolic structures of a main function module (MFM) were designed, and three error detection schemes were developed based on different linear arithmetic codes (LACs). The MFM structures were combined flexibly with the error detection schemes. The time and area overheads of our architecture were analyzed through the implementation in an application-specific integrated circuit (ASIC), while the error detection and location capabilities of our architecture were demonstrated by C++ simulation, in comparison to two existing methods. The results show that our architecture can detect single-bit error (SBE) with 100% accuracy and locate the erroneous processing element (PE), and correctly identify most of the single PE errors and almost all of the multi-PE errors (when there are more than three erroneous PEs). The only weakness of our architecture is the relatively high time and area overhead ratios.

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Section: Introductionmentioning

confidence: 99%

A Secure Architecture for Modular Division over a Prime Field against Fault Injection Attacks

Qin

2020

Applied Sciences

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“…To get away with permanent latent fault issue in one of the replicas, one must use N-Modular Redundancy (NMR) or other similar techniques [2], [4], [5] which have significant area overhead. To compensate for huge area overhead of concurrent NMR scheme, several encoding schemes have been proposed in the literature such as weight-based codes [6], Berger codes [7], Bose-Lin codes [8], etc. Even though, they are effective codes for detecting faults, they detect those faults that are excited and observed at the output.…”

Section: Introductionmentioning

confidence: 99%

Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates

Parvin

Altun

2019

IEEE Access

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Reversible logic has 100% fault observability meaning that a fault in any circuit node propagates to the output stage. In other words, reversible circuits are latent-fault-free. Our motivation is to incorporate this unique feature of reversible logic to design CMOS circuits having perfect or 100% Concurrent Error Detection (CED) capability. For this purpose, we propose a new fault preservative reversible gate library called Even Target-Mixed Polarity Multiple Control Toffoli (ET-MPMCT). By using ET-MPMCT, we ensure that the evenness/oddness of applied 1's at input, is preserved at all levels of a circuit including output level unless there is a faulty node. A single fault always destroys the parity of input at the output. Our design strategy has two steps for a given function: 1) implement the function with our proposed reversible ET-MPMCT gate library; and 2) apply reversible-to-CMOS gate conversion. For the first step, we propose two approaches. For our first approach in step 1, we first need to have a reversible form of the given function if it is irreversible. Then, synthesize the reversible function using Mixed Polarity Multiple Control Toffoli (MPMCT) gate library by conventional reversible logic synthesis techniques. Finally, the synthesized circuit is converted to ET-MPMCT constructed circuit which is fault preservative. Our second approach, is an ESOP-Exclusive Sum of Products-based synthesis approach modified for our proposed fault preservative ET-MPMCT gate library. It does work with both irreversible and reversible functions. We synthesize our circuits with both approaches in step 1 and choose the circuit with lower number of reversible gates to be fed to step 2 of our design strategy. In second step of our design strategy, we convert our fault preservative reversible circuits into their CMOS counterparts. The performance of our designs is compared with other CED schemes in the literature in terms of area, power consumption, delay and detection rate. Simulations are done with Cadence Genus tool using TSMC 40nm technology. Clearly, results are in favor of our proposed techniques.

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“…Examples of information redundant codes frequently used are Residue Codes [3] and Parity checking [4], which can only detect single errors. Berger Code [5] provides a 100% coverage of all multiple bit errors, but can incur large area overheads when used in applications which require the detection of some, but not all, multiple bit errors. Dong's Code [6] however, permits the coverage of multiple bit errors to be tailored to a given application, thus minimising area overheads incurred.…”

Section: Introductionmentioning

confidence: 99%

A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor

Marshall¹,

Russell²

2007

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007)

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As a result of advances in technology shrinking device dimensions, the occurrence of transient errors is increasing. This together with the concomitant reduction in supply voltages has decreased noise margins causing system reliability to be reduced, at a time when electronic systems are being used increasingly in 'safety critical' applications. Previous work has demonstrated that an information redundant Concurrent Error Detection (CED) scheme using Dong's Code can be applied efficiently to a processor using an asynchronous design style incurring area overheads of approximately 12% [1] when placed on silicon. This paper furthers the above work by extending the capabilities of the processor to include the multiplication function also guarded by a CED scheme, permitting the processor to be used in a wider range of applications; e.g. DSP. The paper also demonstrates that a reduction in power of 22% can be achieved by utilising an asynchronous design style rather than its synchronous counterpart. Furthermore, the power overhead for the asynchronous CED processor was found to be 5% less than that of the synchronous processor without CED. Asynchronous design style is also known to have the inherent benefit of not requiring difficult to design, global timing clock trees and networks. Previous work has also demonstrated that approximately, 25% area savings can be made when comparing Dong's Code to a Berger Code CED scheme on the multiplier function [2]. Through the implementation of a larger number of operations within the ALU, all protected by the same information redundant code, further savings can be made through reuse of common blocks, as codes often share many similarities within their prediction equations. With lower power dissipation and a reduced area overhead, compared to its synchronous counterpart, this makes the asynchronous CED circuit attractive and viable for reliable mobile computation. This paper also extends the work with the implementation of a synchronous and asynchronous processor, with and without CED on a FPGA.

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Concurrent error detection in arithmetic and logical operations using Berger codes

Cited by 25 publications

References 8 publications

A Secure Architecture for Modular Division over a Prime Field against Fault Injection Attacks

A Secure Architecture for Modular Division over a Prime Field against Fault Injection Attacks

Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates

A Low Power Information Redundant Concurrent Error Detecting Asynchronous Processor

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