Conduction behaviour of low-temperature (≤600°C) polysilicon TFTs with an in situ drain doping level

Pichon, Laurent; Raoult, F.; Bonnaud, Olivier; Sehil, H.; Briand, D.

doi:10.1016/0038-1101(94)00277-m

Cited by 14 publications

(13 citation statements)

References 14 publications

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“…This suggests that the electrical conduction could result from a field-enhanced type thermal emission. Indeed, it is worth to notice that accordingly to the plots of the figure 6.b, the electrical behaviour of the off-state current of the monolayer-poly-Si TFTs is similar to that of hydrogenated bilayer-poly-Si TFTs previously studied [26]. In this case we observed a decrease of the activation energy of the corresponding current at high drain and gate voltages, and a decreasing thermal dependence of the current when the temperature decreases.…”

Section: Introductionsupporting

confidence: 79%

“…6 we plot the I ds versus V ds curve in a semi-logarithmic scale. In the monolayer-poly-Si TFTs, at gate voltages V gs <-6V ( fig 6b) the linearity of the curves shows that the Off state conduction obeys the former relationship by approaching the local electric field only by its lateral component indicating that in our case the drain voltage is mainly responsible for the lowering of the energy barrier E i at the grain boundary as it has been previously observed [26]. Let us note that the plot of the I ds versus F does not lead to a linear curve, that confirms the previous explanation.…”

Section: Introductionsupporting

confidence: 77%

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Thin film transistors fabricated by in situ doped unhydrogenated polysilicon films obtained by solid phase crystallization

Pichon

Mourgues

Raoult

et al. 2001

Semicond. Sci. Technol.

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High-mobility low-temperature ( 600 • C) unhydrogenated in situ doped polysilicon thin film transistors (TFTs) are made. Polysilicon layers are grown by a low pressure chemical vapour deposition (LPCVD) technique and crystallized in a vacuum by thermal annealing. The source and drain regions are in situ doped. The gate insulator is made of an atmospheric pressure chemical vapour deposition (APCVD) silicon dioxide. Hydrogen passivation is not performed on the transistors. One type of transistor is made of two polysilicon layers, the other one is fabricated from a single polysilicon layer. The electrical properties are better for transistors made of a single polysilicon layer: a low threshold voltage (1.2 V), a subthreshold slope S = 0.7 V/dec, a high field effect mobility (≈100 cm 2 V −1 s −1 ) and an on/off-state current ratio higher than 10 7 for a drain voltage V ds = 1 V. At low drain voltage, for both transistors, the off-state current results from a pure thermal emission of trapped carriers. However, at high drain voltage, the electrical behaviour is different: in the case of single polysilicon TFTs, the current obeys the field-assisted (Poole-Frenkel) thermal emission model of trapped carriers while for TFTs made of two polysilicon layers, the higher off-state current results from a field-enhanced thermal emission.

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Section: Introductionsupporting

confidence: 79%

Section: Introductionsupporting

confidence: 77%

Thin film transistors fabricated by in situ doped unhydrogenated polysilicon films obtained by solid phase crystallization

Pichon

Mourgues

Raoult

et al. 2001

Semicond. Sci. Technol.

Self Cite

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“…In addition, the electron field effect mobility in poly-Si for planar TFTs crystallized by SPC technique reaches easily 100 cm 2 /Vs (13).…”

Section: Ecs Transactions 22 (1) 293-304 (2009)mentioning

confidence: 99%

Vertical Channel Thin Film Transistor Technology: Similar Approach with 3D-ULSI Monolithic Technology

Bonnaud

2009

ECS Trans.

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The previous thin film transistor studies involved planar process that means channel parallel to the substrate surface. Another way passes by a modification of the spatial geometry, more especially by the creation of vertical channels. This allows an increase of the equivalent current density flowing in the circuit thanks to two major modifications, the channel length that can be much shorter and the channel width that can be much higher, for the same design rules and for the same substrate area. The approach is thus similar to the recent evolution of the monolithic silicon technology. After the presentation of the interest of such vertical channel ways on both ULSI and thin film technologies, results on vertical TFTs are presented and discussed. We finally give comments on the common approaches between nano-and giga-electronics involving three dimensional geometry, in order to show that their basic scientific principles are roughly the same.

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“…To control the doping of the film, doping gases can be introduced in the reactor during the deposition, diborane (B2H6) for p-type semiconductor and phosphine (PH3) or arsine (AsH3) for n-type; these steps are called in-situ doping technique 27 . With the goal to improve the electrical characteristics, after the deposition of the film, the silicon is crystallized either by solid phase crystallization (SPC) at 600°C during several hours, in the same reactor [28][29] or by laser crystallization 30 . This last technique, even though it has proved some very good potentialities [30][31] , is less adapted to the large area electronics, mainly in reason of the low flow of fabrication, of its high cost and of the difficulty to reach a good homogeneity of the crystallized films.…”

Section: Low Temperature Process Backgroundmentioning

confidence: 99%

Vertical Conduction in the New Field Effect Transistors: p-Type and n-Type Vertical Channel Thin Film Transistors

Bonnaud

Zhang

2014

Int. J. Hi. Spe. Ele. Syst.

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In order to pursue the integration, the research activities were oriented during the last years towards channel conduction in a plan perpendicular to the substrate surface while in the traditional architectures the conduction is parallel to the surface, under the gate. In the integrated technologies, this approach led to the FinFET. But in this case, even though the conduction plan is perpendicular to the substrate surface, the direction of the drain currents remains parallel to the substrate. New electronics devices were designed with the channels vertically oriented. In the monolithic technologies, many drawbacks have stopped this trend. However, in the case of thin film technologies, the approach appeared more suitable. The channel conduction is thus vertically oriented. But a drawback comes from the leakage current flowing between source and drain. The introduction of an insulating barrier in-between and the decrease of the thickness of the channel active layer, led to electrical behavior much more suitable for applications. After an overview of the different approaches developed as well in monolithic technologies as in thin film technologies, this presentation will give details on the concept and on the fabrication process of quasi-vertical thin film transistors. The associated electrical results will be described, analyzed and commented.

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Conduction behaviour of low-temperature (≤600°C) polysilicon TFTs with an in situ drain doping level

Cited by 14 publications

References 14 publications

Thin film transistors fabricated by in situ doped unhydrogenated polysilicon films obtained by solid phase crystallization

Thin film transistors fabricated by in situ doped unhydrogenated polysilicon films obtained by solid phase crystallization

Vertical Channel Thin Film Transistor Technology: Similar Approach with 3D-ULSI Monolithic Technology

Vertical Conduction in the New Field Effect Transistors: p-Type and n-Type Vertical Channel Thin Film Transistors

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