Thin film transistors fabricated by in situ doped unhydrogenated polysilicon films obtained by solid phase crystallization

Abstract

High-mobility low-temperature ( 600 • C) unhydrogenated in situ doped polysilicon thin film transistors (TFTs) are made. Polysilicon layers are grown by a low pressure chemical vapour deposition (LPCVD) technique and crystallized in a vacuum by thermal annealing. The source and drain regions are in situ doped. The gate insulator is made of an atmospheric pressure chemical vapour deposition (APCVD) silicon dioxide. Hydrogen passivation is not performed on the transistors. One type of transistor is made of two polysilicon layers, the other one is fabricated from a single polysilicon layer. The electrical properties are better for transistors made of a single polysilicon layer: a low threshold voltage (1.2 V), a subthreshold slope S = 0.7 V/dec, a high field effect mobility (≈100 cm 2 V −1 s −1 ) and an on/off-state current ratio higher than 10 7 for a drain voltage V ds = 1 V. At low drain voltage, for both transistors, the off-state current results from a pure thermal emission of trapped carriers. However, at high drain voltage, the electrical behaviour is different: in the case of single polysilicon TFTs, the current obeys the field-assisted (Poole-Frenkel) thermal emission model of trapped carriers while for TFTs made of two polysilicon layers, the higher off-state current results from a field-enhanced thermal emission.

Low frequency noise in polysilicon thin film transistors: effect of the laser annealing of the active layer

“…[7], and µ is calculated from the transconductance g m = dI DS /dV GS measured in the linear mode. The reported values of α are higher than in crystalline silicon (c-Si) MOS transistors (in ref [7] 10 -6 < α < 10 -2 ), because of a higher defect density in polysilicon TFTs corresponding to Ω/Ω eff > 1 in (5). In addition, plots of Fig.…”

“…More details for fabrication are given in Refs. [5] and [6]. For LPC TFTs process laser annealing parameters (P = 4.8 W, v = 70 mm/s) were adjusted to limit contamination from the glass substrate of the active layer.…”

“…In addition, a high surface roughness and a contamination from the glass substrate are possible as reported in such laser annealed polysilicon layer [6]. In such case the average grain size in laser annealed polysilicon layer is quite the same as for FSPC annealed polysilicon layers (~ 100 nm [5,6]). …”

P-type and N-type multi-gate polycrystalline silicon vertical thin film transistors based on low-temperature technology

“…At these conditions, the films are still in amorphous state [10]; therefore a solid phase crystallization step (SPC) is carried out at 600°C for 12 hours to crystallize the amorphous silicon into polysilicon. The combined techniques of LPCVD and SPC have been adopted in the lateral TFTs fabrication, combination that was proved to be a way to obtain a high field effect mobility of carriers higher than 100 cm 2 /V·s with an I ON /I OFF of more than 10 6 [11]. Therefore, this technology will also be used in our vertical TFTs fabrication.…”

Thermal dependence of low-frequency noise in polysilicon thin film transistors

“…Finally the devices were annealed into forming gas (N 2 /H 2 =95%) at 390°C. More details for fabrication are given in ref [4].…”