International audienceUp-scaling silicon nanowire (SiNW)-based functionalities requires a reliable strategy to precisely position and integrate individual nanowires. We here propose an all-in-situ approach to fabricate self-positioned/aligned SiNW, via an in-plane solid-liquid-solid growth mode. Prototype field effect transistors, fabricated out of in-plane SiNWs using a simple bottom-gate configuration, demonstrate a hole mobility of 228 cm2/V s and on/off ratio >103. Further insight into the intrinsic doping and structural properties of these structures was obtained by laser-assisted 3 dimensional atom probe tomography and high resolution transmission electron microscopy characterizations. The results could provide a solid basis to deploy the SiNW functionalities in a cost-effective way

International audienceSilicon nanowires (SiNWs) are synthesized following two methods: i) the VLS (Vapor-Liquid-Solid) growth technique (bottom up approach), and ii) the sidewall spacer fabrication (top down approach) commonly used in microelectronic industry. The VLS growth technique uses gold nanoparticles to activate the vapor deposition of the precursor gas and to initiate 100 nm diameter SiNWs network growth. In the case of the sidewall spacer method, a polysilicon layer is deposited by LPCVD (Low Pressure Chemical Vapor Deposition) technique on SiO2 wall patterned by conventional UV lithography technique. Polysilicon film is then plasma etched. Accurate control of the etching rate leads to the formation of spacers with a 100 nm curvature radius that can be used as polysilicon NWs. Each kind of nanowires is integrated into resistors fabrication. Electrical measurements show the potential use of these SiNWs based resistors as gas sensors for ammonia (NH3) and smoke detection

Despite the remarkable optoelectronic properties of halide perovskites, achieving reproducible field effect transistor (FET) action in polycrystalline films at room temperature has been challenging and represents a fundamental bottleneck for understanding electronic charge transport in these materials. In this work, we report halide perovskite-based FET operation at room temperature with negligible hysteresis. Extensive measurements and device modeling reveal that incorporating high-k dielectrics enables modulation of the channel conductance. Furthermore, continuous bias cycling or resting allows dynamical reconfiguration of the FETs between p-type behavior and ambipolar FET with balanced electron and hole transport and an ON/OFF ratio up to 10 4 and negligible degradation in transport characteristics over 100 cycles. These results elucidate the path for achieving gate modulation in perovskite thin films and provide a platform to understand the interplay between the perovskite structure and external stimuli such as photons, fields, and functional substrates, which will lead to novel and emergent properties.