Conductivity behavior in polycrystalline semiconductor thin film transistors

Abstract

CdSe thin film transistor (TFT) structures which have been ion implanted with 50 keV 52Cr, 50 keV 27Al, or 15 keV 11B have a very steeply rising conductivity above some threshold dose and exhibit modulated transistor characteristics over certain ranges of implant dose, even though there is no thermal annealing during or after ion implantation. These results are interpreted using a model based on grain boundary trapping theory. The dependence of leakage current on implant dose, and of drain current (at a fixed dose) on gate voltage are described very well by this model, when the drain voltage is very small. Using this simple model, the important parameters of the polycrystalline CdSe film, namely the trap density per unit area in the grain boundary, the donor density, grain size, and electron mobility can be deduced. The effect of thermal annealing on implanted and unimplanted CdSe TFT’s has also been studied and the model appears to give a general description of the conductivity behavior in polycrystalline semiconductor TFT’s. This is illustrated by applying the model to devices fabricated by other groups from polycrystalline CdSe, poly-Si and laser-annealed poly-Si semiconductor layers.

Stress Power Dependent Self-Heating Degradation of Metal-Induced Laterally Crystallized n-Type Polycrystalline Silicon Thin-Film Transistors

“…For low and high power stresses, it is seen that the most dramatic degradation occurs at the pseudosubthreshold region [19], clearly resulting in SS, V th , and I on degradation. I on degradation is reduced at the higher V g region due to the V g -induced GB barrier lowering effect [20]- [22]. It is noted that I on degradation symmetrically occurs for forward and reverse measurement modes, implying that such SH stress biases cause uniform degradation along the entire TFT channel.…”

“…where ε s is the Si permittivity, and d is the channel layer [21] or the inversion layer thickness [20], [22]. Therefore, by plotting ln µ eff ∼ −1/V gt , S of stressed devices at different stress times can be extracted from the slope of the plot, as shown in Fig.…”

Single-electron effects in heavily doped polycrystalline silicon nanowires

“…The differences in electrical behavior between polycrystalline and crystalline silicon wires of nominally identical geometry suggest a strong influence from polysilicon grain boundaries, which will contain a high concentration of electrically active defect states, segregated dopants, and other impurities. 10,11 Large numbers of carriertrapping states pin the Fermi level even for high doping levels, 12 creating a potential barrier at the grain boundary. Pinning of the Fermi level strongly attenuates gate action in polysilicon films 13 and the defect states provide an electrostatic screening mechanism.…”

One-dimensional simulation study of microcrystalline silicon thin films for solar cell and thin film transistor applications using AMPS-1D

“…The column boundaries in Ac-Si:H TFTs can be studied by using the Levinson technique (the trap density can be estimated from the drain current as a function of gate voltage using this technique) [17] as given in Eq. (1).…”