Configurable Fault-Tolerance for a Configurable VLIW Processor

Anjam, Fakhar; Wong, Stephan

doi:10.1007/978-3-642-36812-7_16

Cited by 7 publications

(3 citation statements)

References 8 publications

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“…The proposed approach is applied over a VLIW processor, which has a fixed issue-width during execution, defined at design-time, running a single application. Dynamically reconfigurable and fault tolerant VLIWs, such as [15], where several applications are executed in parallel, is left as future work. Fig.…”

Section: Intra-cluster Dynamic Mechanismmentioning

confidence: 99%

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Dynamic fault-tolerant VLIW processor with heterogeneous Function Units

Psiakis

Kritikakou

Sentieys

2022

Microprocessors and Microsystems

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Section: Intra-cluster Dynamic Mechanismmentioning

confidence: 99%

“…As shown in the experimental results, the average ILP of ten benchmarks on a VLIW processor having 4 issues is 2. 15 (more details in Table 7 -Section 5). Therefore, the idle FUs can be used to execute the replicated instructions, reducing the negative impact of SW redundancy on the execution time.…”

Section: Introductionmentioning

confidence: 99%

Dynamic fault-tolerant VLIW processor with heterogeneous Function Units

Psiakis

Kritikakou

Sentieys

2022

Microprocessors and Microsystems

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“…First concepts involving coarse-grained lockstepping are promising [18]- [20], but do not address the specific challenges to FT in space [21]. FT using thread-level very-long-instruction word architectures [22], [23] has also been explored, though the approach still requires pipelinelevel voters in hardware. Most implement checkpoint & rollback or restart, which makes them unsuitable for spacecraft command & control applications [24], others ignore fault-detection [25], [26], or require external, infallible fault detection entities with deep knowledge about application-intrinsics [27] but no concept of how this could be obtained.…”

Section: Related Workmentioning

confidence: 99%

Bringing Fault-Tolerant GigaHertz-Computing to Space: A Multi-stage Software-Side Fault-Tolerance Approach for Miniaturized Spacecraft

Fuchs

Stefanov

Murillo

et al. 2017

2017 IEEE 26th Asian Test Symposium (ATS)

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Modern embedded technology is a driving factor in satellite miniaturization, contributing to a massive boom in satellite launches and a rapidly evolving new space industry. Miniaturized satellites, however, suffer from low reliability, as traditional hardware-based fault-tolerance (FT) concepts are ineffective for on-board computers (OBCs) utilizing modern systems-on-a-chip (SoC). Therefore, larger satellites continue to rely on proven processors with large feature sizes. Software-based concepts have largely been ignored by the space industry as they were researched only in theory, and have not yet reached the level of maturity necessary for implementation. We present the first integral, real-world solution to enable fault-tolerant general-purpose computing with modern multiprocessor-SoCs (MPSoCs) for spaceflight, thereby enabling their use in future high-priority space missions. The presented multi-stage approach consists of three FT stages, combining coarse-grained thread-level distributed self-validation, FPGA reconfiguration, and mixed criticality to assure long-term FT and excellent scalability for both resource constrained and critical high-priority space missions. Early benchmark results indicate a drastic performance increase over state-of-the-art radiation-hard OBC designs and considerably lower software-and hardware development costs. This approach was developed for a 4-year European Space Agency (ESA) project, and we are implementing a tiled MPSoC prototype jointly with two industrial partners.

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