Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes

Studer, Christoph; Preyss, Nicholas; Roth, Christoph; Burg, Andreas

doi:10.1109/acssc.2008.5074592

Cited by 38 publications

(35 citation statements)

References 11 publications

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“…Our architecture improves the architecture presented in [5], which we will briefly review below. With the OMS algorithm, instead of calculating a different minimum, which is used in (4), for each one of the variable nodes to which a layer is connected, it suffices to find the two smallest values, denoted m1 and m2.…”

Section: A Reference Architecturementioning

confidence: 99%

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A parallelized layered QC-LDPC decoder for IEEE 802.11ad

Balatsoukas‐Stimming

Preyss

Cevrero

et al. 2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

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Abstract-We present a doubly parallelized layered quasi-cyclic lowdensity parity-check decoder for the emerging IEEE 802.11ad multigigabit wireless standard. The decoding algorithm is equivalent to a nonparallelized layered decoder and, thus, retains its favorable convergence characteristics, which are known to be superior to those of flooding schedule based decoders. The proposed architecture was synthesized using a TSMC 40 nm CMOS technology, resulting in a cell area of 0.18 mm 2 and a clock frequency of 850 MHz. At this clock frequency, the decoder achieves a coded throughput of 3.12 Gbps, thus meeting the throughput requirements when using both the mandatory BPSK modulation and the optional QPSK modulation.

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Section: A Reference Architecturementioning

confidence: 99%

“…Our architecture adds a level of parallelism to the reference architecture of Studer et al [5] by carefully splitting the parity-check matrix of the codes into parts, without any sacrifice in terms of convergence speed.…”

Section: Introductionmentioning

confidence: 99%

A parallelized layered QC-LDPC decoder for IEEE 802.11ad

Balatsoukas‐Stimming

Preyss

Cevrero

et al. 2013

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS)

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“…Table II compares the implementation result of our decoder with existing 802.11n LDPC decoders from [3], [4], [6]. The solutions from [3], [4], [6] are all based on the conventional single-layer decoding architecture. As a fair comparison, the areas of those designs are all normalized to 45nm technology.…”

Section: Vlsi Implementation and Comparisonmentioning

confidence: 99%

“…we can employ Z parallel check node processors to process Z rows in parallel. With this amount of parallelism, the conventional layered decoder can typically offer 100-1000 Mbps throughput [3], [4], [5], [6].…”

Section: Introductionmentioning

confidence: 99%

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Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes

Sun

Wang

Cavallaro

2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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Abstract-We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The maximum number of rows that can be simultaneously processed by the conventional layered decoder is limited to the sub-matrix size. To remove this limitation and support layer-level parallelism, we extend the conventional layered decoding algorithm and architecture to enable simultaneously processing of multiple (K) layers of a parity check matrix, which will lead to a roughly K-fold throughput increase. As a case study, we have designed a double-layer parallel LDPC decoder for the IEEE 802.11n standard. The decoder was synthesized for a TSMC 45-nm CMOS technology. With a synthesis area of 0.81 mm 2 and a maximum clock frequency of 815 MHz, the decoder achieves a maximum throughput of 3.0 Gbps at 15 iterations.

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Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

Roberts¹,

Kumari

Anguraj³

2021

Int J Communication

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Summary Information theory coding is an impressive and most celebrated field of research that has spawned numerous extremely important solutions to the intractable problems of secure data communications. Recent advancements in error control coding methods have seen a huge surge in using low‐density parity‐check (LDPC) code‐based decoding algorithms to solve imperative issues related to reliable data transmission and reception. Till date, extensive research efforts have been consistently being made on LDPC codes which focus on algorithm‐driven and hardware‐realization‐based approaches. The main intension of this research work is to provide an extensive systematic elucidation on the recent advancements in LDPC decoding algorithms. In addition, a thorough performance evaluation and analysis of several outstanding LDPC decoding techniques is presented. Finally, conclusions are drawn by summarizing the important research findings, interesting open problems, current challenges and broader perspectives for future directions of research.

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Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes

Cited by 38 publications

References 11 publications

A parallelized layered QC-LDPC decoder for IEEE 802.11ad

A parallelized layered QC-LDPC decoder for IEEE 802.11ad

Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes

Certain investigations on recent advances in the design of decoding algorithms using low‐density parity‐check codes and its applications

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