Configurable Transactional Memory

Murphy, Chris; Lindquist, Daniel; Rynning, Ann Marie; Cecil, T.; Leavitt, Sarah; Chang, Mark L.

doi:10.1109/fccm.2007.41

Cited by 34 publications

(12 citation statements)

References 5 publications

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“…when resources are exceeded) [7]. ATLAS and later Configurable TM were the first systems to support hardware TM on FPGA [8], [9]. Hardware acceleration proposals by using Bloom filters for TM were also investigated [10], [11], as well as Hybrid TM on FPGA [12].…”

Section: Introductionmentioning

confidence: 99%

A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory

Arcas

Kirchhofer

Sönmez

et al. 2012

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

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Abstract-Multi-core prototyping presents a good opportunity for establishing low overhead and detailed profiling and visualization in order to study new research topics. In this paper, we design and implement a low execution, low area overhead profiling mechanism and a visualization tool for observing Transactional Memory behaviors on FPGA. To achieve this, we non-disruptively create and bring out events on the fly and process them offline on a host. There, our tool regenerates the execution from the collected events and produces traces for comprehensively inspecting the behavior of interacting multithreaded programs. With zero execution overhead for hardware TM events, single-instruction overhead for software TM events, and utilizing a low logic area of 2.3% per processor core, we run TM benchmarks to evaluate various different levels of profiling detail with an average runtime overhead of 6%. We demonstrate the usefulness of such detailed examination of SW/HW transactional behavior in two parts: (i) we speed up a TM benchmark by 24.1%, and (ii) we closely inspect transactions to point out pathologies.

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Section: Introductionmentioning

confidence: 99%

A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory

Arcas

Kirchhofer

Sönmez

et al. 2012

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

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“…This makes instruction and data locality arguably less important than efficiently managing the parallelism across many cores. While speculative execution was previously proposed for packet processing [6,7], to our knowledge this paper is the first evaluation with a real system and stateful and controlflow intensive applications. While we do not quantitatively measure the increased ease of programmability of transactional memory for packet processing, we rely on prior efforts to do so in other application domains, e.g.…”

Section: Related Workmentioning

confidence: 99%

“…Transactional memory (TM) [5,6] offers a potential solution to both challenges as it (i) can reduce false contention on critical sections, and (ii) offers an easier programming model for synchronization. A TM system optimistically allows multiple threads inside a critical section-hence TM can improve performance when the parallel critical sections access independent data locations.…”

Section: Introductionmentioning

confidence: 99%

The case for hardware transactional memory in software packet processing

Labrecque

Steffan

2010

Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems

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Software packet processing is becoming more important to enable differentiated and rapidly-evolving network services. With increasing numbers of programmable processor and accelerator cores per network node, it is a challenge to support sharing and synchronization across them in a way that is scalable and easy-to-program. In this paper, we focus on parallel/threaded applications that have irregular control-flow and frequently-updated shared state that must be synchronized across threads. However, conventional lock-based synchronization is both difficult to use and also often results in frequent conservative serialization of critical sections. Alternatively, we propose that Transactional memory (TM) is a good match to software packet processing: it both (i) can allow the system to optimistically exploit parallelism between the processing of packets whenever it is safe to do so, and (ii) is easy-to-use for a programmer. With the NetFPGA [1] platform and four network packet processing applications that are threaded and share memory, we evaluate hardware support for TM (HTM) using the reconfigurable FPGA fabric. Relative to NetThreads [2], our two-processor four-way-multithreaded system with conventional lock-based synchronization, we find that adding HTM achieves 6%, 54% and 57% increases in packet throughput for three of four packet processing applications studied, due to reduced conservative serialization.

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“…Kachris and Kulkarni describe a TM implementation for embedded systems which can work without caches, using a central transactional controller on four Microblaze cores [12]. TM is used as a simple synchronization mechanism that can be used with higher level CAD tools like EDK for non-cache coherent embedded MPSoC.…”

Section: Related Workmentioning

confidence: 99%

TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System

Sönmez

Arcas

Pflucker

et al. 2011

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

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In this paper we present the design and implementation of TMbox: An MPSoC built to explore tradeoffs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTM-ASF proposal on a Virtex-5 FPGA and we accelerate three benchmarks written to investigate TM.

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Configurable Transactional Memory

Cited by 34 publications

References 5 publications

A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory

A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory

The case for hardware transactional memory in software packet processing

TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System

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