Configuration of VLSI Arrays in the Presence of Defects

Abstract

Abstract. The penalties for configuring VLSI arrays for yield enhancement are assessed. Each dement of the fabricated array is assumed to be defective with independent probability p. A fixed fractmn R of the elements are to be connected into a prespecified defect-free configuration by means of switched interconnections. The probability that this can be done, known as the yield, must be bounded away from zero. The additional interconnections required increase the integrated circuit's area by the area overhead ratio AOR.

Behavioral-level synthesis of heterogeneous BISR reconfigurable ASIC's

“…Almost all current day memory designs use BISR techniques [4], as they significantly increase memory production profitability. Programmable logic arrays are another class of bit-sliced devices for which BISR has been well addressed [5], [6]. It has also been successfully applied for arithmetic-logic unit byte slices [1].…”

Yield and Performance Enhancement through Redundancy in VLSI and WSI Multi-Precessor Systems.

“…In addition, internal connections between chips on the same __. *-*S*% J* * The issue of fault-tolerance in VLSI and WSI processing arrays has been the subject of recent studies, e.g., [8], [10], [18], [20], [26], C38], [40], [41]. In these publications, various schemes have been proposed that introduce fault-tolerance into the architecture of processor arrays.…”

“…The hardware added can be in the form of switching elements, (e.g., [8], [38] and [41]) or redundancy in processors or communication links ( e.g., [10], [26]). When carrying out such an analysis we have to 7 take into account the following two parameters:…”

“…For example, in [8], [38] and [41] switching elements are added between processors to assist in achieving this goal. In [10] and [26] connecting tracks are added on the wafer to be used in bypassing the defective PEs when connecting the fault-free ones. However, the silicon area that needs to be devoted to switching elements (e.g., switches capable of interconnecting 4 to 8 separate parallel busses [41]) or to additional communication links cannot be ignored.…”

Modeling the Effect of Redundancy on Yield and Performance of VLSI Systems

“…Hence [21, [18], [15] and! or redundant processors, communication links, or other system elements [3], [10], [6]. When carrying out such an analysis we have to take into account the relative hardware complexity (silicon area) of all system elements, and their susceptibility to failures (manufacturing defects or operational faults).…”