Confined Epitaxial Lateral Overgrowth (CELO): A novel concept for scalable integration of CMOS-compatible InGaAs-on-insulator MOSFETs on large-area Si substrates

Czornomaz, Lukas; Uccelli, Emanuele; Sousa, Marilyne; Deshpande, V.; Djara, V.; Caimi, Daniele; Rossell, Marta D.; Erni, Rolf; Fompeyrine, J.

doi:10.1109/vlsit.2015.7223666

Cited by 64 publications

(49 citation statements)

References 4 publications

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“…Recently, an alternative to the ART technique known as the conined epitaxial lateral overgrowth (CELO) technique [132] has been developed. This method begins with the formation of a 3D cavity in an oxide containing a crystalline seed.…”

Section: Lau Progress In Crystal Growth and Characterization Of Matmentioning

confidence: 99%

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Lau

2017

Progress in Crystal Growth and Characterization of Materials

125

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Please note: Changes made as a result of publishing processes such as copy-editing, formatting and page numbers may not be reflected in this version. For the definitive version of this publication, please refer to the published source. You are advised to consult the publisher's version if you wish to cite this paper.This version is being made available in accordance with publisher policies. See http://orca.cf.ac.uk/policies.html for usage policies. Copyright and moral rights for publications made available in ORCA are retained by the copyright holders. U N C O R R E C T E D P R O O F ARTICLE INFO ABSTRACTMonolithic integration of III-V on silicon has been a scientifically appealing concept for decades. Notable progress has recently been made in this research area, fueled by significant interests of the electronics industry in high-mobility channel transistors and the booming development of silicon photonics technology. In this review article, we outline the fundamental roadblocks for the epitaxial growth of highly mismatched III-V materials, including arsenides, phosphides, and antimonides, on (001) oriented silicon substrates. Advances in hetero-epitaxy and selective-area hetero-epitaxy from micro to nano length scales are discussed. Opportunities in emerging electronics and integrated photonics are also presented.

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Section: Lau Progress In Crystal Growth and Characterization Of Matmentioning

confidence: 99%

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Lau

2017

Progress in Crystal Growth and Characterization of Materials

125

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“…A key issue for good device performance is the overall defect control . An alternative to the ART technique is called Confined Epitaxial Lateral Overgrowth (CELO) . The main concept, illustrated in Fig.…”

Section: Ge‐based Technologiesmentioning

confidence: 99%

“…Process flow for the integration of lattice mismatched materials on insulator on Si by the CELO method .…”

Section: Ge‐based Technologiesmentioning

confidence: 99%

Technology development challenges for advanced group IV semiconductor devices

Claeys¹,

Arimura²,

Collaert³

et al. 2016

Physica Status Solidi (a)

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Advanced devices are not only driven by minimum device geometry, performance enhancement, and cost issues, but also require a low power consumption. Device scaling for higher performance and lower power consumption necessitates the introduction of advanced process modules, new materials new device architectures and, finally, even the use of alternative device operation principles compared to the standard MOS transistor. Several of these advanced devices will be discussed in view of their scalability and their potential for coping with the ITRS roadmap. Key performance parameters will be investigated.

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“…As the CMOS IC industry moves into the sub-20 nm technology regime, FinFET technologies have shown significant promise [4] (alongside FDSOI [5]), and the aspect ratio trapping technique has been shown to enable the integration of high mobility channel materials onto a 300 mm silicon platform in a fin configuration [6,7]. Much attention has now turned to tri-gate devices with III-V channels.…”

Section: Introductionmentioning

confidence: 99%

InAs FinFETs With H_finnm Fabricated Using a Top–Down Etch Process

Oxland

Chang

et al. 2016

IEEE Electron Device Lett.

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Confined Epitaxial Lateral Overgrowth (CELO): A novel concept for scalable integration of CMOS-compatible InGaAs-on-insulator MOSFETs on large-area Si substrates

Cited by 64 publications

References 4 publications

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Technology development challenges for advanced group IV semiconductor devices

InAs FinFETs With H_finnm Fabricated Using a Top–Down Etch Process

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Confined Epitaxial Lateral Overgrowth (CELO): A novel concept for scalable integration of CMOS-compatible InGaAs-on-insulator MOSFETs on large-area Si substrates

Cited by 64 publications

References 4 publications

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Epitaxial growth of highly mismatched III-V materials on (001) silicon for electronics and optoelectronics

Technology development challenges for advanced group IV semiconductor devices

InAs FinFETs With Hfinnm Fabricated Using a Top–Down Etch Process

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Product

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InAs FinFETs With H_finnm Fabricated Using a Top–Down Etch Process