Conformable formation of high quality ultra-thin amorphous Ta/sub 2/O/sub 5/ gate dielectrics utilizing water assisted deposition (WAD) for sub 50 nm damascene metal gate MOSFETs

Inumiya, Seiji; Morozumi, Yuichiro; Yagishita, Akira; Saito, Tomohiro; Gao, De; Choi, Do‐Young; Hasebe, Kazuhide; Suguro, K.; Tsunashima, Y.; Arikado, T.

doi:10.1109/iedm.2000.904403

Cited by 4 publications

References 3 publications

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High Quality Ultrathin La2O3 Films for High-k Gate Insulator

Ohmi

Kobayashi

Aizawa

et al. 2001

31st European Solid-State Device Research Conference

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Properties of amorphous Lanthanum oxide (La 2 O 3 ) film deposited by e-beam evaporationwere investigated by fabricating MIS capacitors. Equivalent oxide thicknesses of 0.8 -1.2 nm were successfully obtained. It was found that the surface morphology of La 2 O 3 thin films is greatly improved by increasing the deposition temperature.The leakage current density was dramatically reduced by post deposition anneal at 400 -600°C. The leakage currents, for example, were as small as 5.5 x 10 -4 A/cm 2 @ EOT=0.88 nm, and 1.7 x 10 -8 A/cm 2 @ EOT=1.26 nm, both at V g =1 V, for n-type Si substrate MIS capacitors.

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High Quality Ultrathin La2O3 Films for High-k Gate Insulator

Ohmi

Kobayashi

Aizawa

et al. 2001

31st European Solid-State Device Research Conference

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Plasma charging effect on MOS devices with gate dielectrics using high dielectric constant material

Tzeng

Chang

Chang‐Liao

7th International Symposium on Plasma- And Process-Induced Damage

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Performance improvement of metal gate CMOS technologies

Matsuda

Yamakawa

Azuma

et al.

2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184)

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Metal gate CMOS technologies for high speed application was investigated using damascene metal gate process [I]. We demonstrated the performance improvement by no gate depletion effect of metal gate using actual device. TVW was used as single work function metal gate material and ultra shallow buried channel profile was formed for threshold voltage control. Self-aligned channel structure effectively reduces source/drain junction capacitance. Extremely good metaVSi02. interface with CVD-TiN gate stack realizes intrinsic channel mobility. Propagation delay time of CMOS inverter ring oscillator was 20 ps, and projected performance in next generation would be better using improved technologies.

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Conformable formation of high quality ultra-thin amorphous Ta/sub 2/O/sub 5/ gate dielectrics utilizing water assisted deposition (WAD) for sub 50 nm damascene metal gate MOSFETs

Cited by 4 publications

References 3 publications

High Quality Ultrathin La2O3 Films for High-k Gate Insulator

High Quality Ultrathin La2O3 Films for High-k Gate Insulator

Plasma charging effect on MOS devices with gate dielectrics using high dielectric constant material

Performance improvement of metal gate CMOS technologies

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