Conformal low -temperature dielectric deposition process below 200&amp;#x00B0;C for TSV application

Praveen, Sampath Kumar; Tsan, Ho Wai; Nagarajan, Rajamani

doi:10.1109/eptc.2010.5702600

Search citation statements

Order By: Relevance

Paper Sections

Select...

Tsv Liner Deposition1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2011

2016

Publication Types

Select...

Article2

Other1

Relationship

Self Cite0

Independent3

Authors

Journals

Cited by 3 publications

(1 citation statement)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…It can be done either by using high temperature thermal oxide deposition or by plasma enhanced chemical vapor deposition (PECVD) with the use of silane and tetrathylorthosilicate (TEOS). 35,36 There is wide application of Sub-atmospheric CVD (SACVD) of Ozone (O3)-TEOS as liner in TSV formation. [37][38][39] Different TSV approaches have different requirements.…”

Section: Tsv Liner Depositionmentioning

confidence: 99%

Heterogeneous 2.5D integration on through silicon interposer

Zhang¹,

Lin²,

Wickramanayaka³

et al. 2015

Applied Physics Reviews

130

View full text Add to dashboard Cite

Section: Tsv Liner Depositionmentioning

confidence: 99%

Heterogeneous 2.5D integration on through silicon interposer

Zhang¹,

Lin²,

Wickramanayaka³

et al. 2015

Applied Physics Reviews

130

View full text Add to dashboard Cite

Notice of Withdrawal Integration of low temperature PECVD deposited silicon oxides with advanced packaging

Wang

Lee

Wang

et al. 2016

2016 IEEE 18th Electronics Packaging Technology Conference (EPTC)

View full text Add to dashboard Cite

Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration

Tzeng

Lau

et al. 2011

International Symposium on Microelectronics

View full text Add to dashboard Cite

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu-plating of blind TSVs on 300mm wafers for 3D integration are investigated. Emphases are placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, leakage currents of the fabricated Cu-filled TSVs are measured. Furthermore cross sections and SEM of the fabricated TSVs are provided and examined.

show abstract

Conformal low -temperature dielectric deposition process below 200°C for TSV application

Cited by 3 publications

References 3 publications

Heterogeneous 2.5D integration on through silicon interposer

Heterogeneous 2.5D integration on through silicon interposer

Notice of Withdrawal Integration of low temperature PECVD deposited silicon oxides with advanced packaging

Oxide Liner, Barrier and Seed Layers, and Cu-Plating of Blind Through Silicon Vias (TSVs) on 300mm Wafers for 3D IC Integration

Contact Info

Product

Resources

About