Congestion-aware power grid optimization for 3D circuits using MIM and CMOS decoupling capacitors

Abstract

Abstract-In three-dimensional (3D) chips, the amount of supply current per package pin is significantly more than in two-dimensional (2D) designs. Therefore, the power supply noise problem, already a major issue in 2D, is even more severe in 3D. CMOS decoupling capacitors (decaps) have been used effectively for controlling power grid noise in the past, but with technology scaling, they have grown increasingly leaky. As an alternative, metal-insulator-metal (MIM) decaps, with high capacitance densities and low leakage current densities, have been proposed. In this paper, we explore the tradeoffs between using MIM decaps and traditional CMOS decaps, and propose a congestion-aware 3D power supply network optimization algorithm to optimize this tradeoff. The algorithm applies a sequence-of-linear-programs based method to find the optimum tradeoff between MIM and CMOS decaps. Experimental results show that power grid noise can be more effectively optimized after the introduction of MIM decaps, with lower leakage power and little increase in the routing congestion, as compared to a solution using CMOS decaps only.

Physical design tradeoffs in power distribution networks for 3-D ICs

“…Considering that a TSV consumes silicon area, the density and dimensions of this novel type of interconnect are greatly restricted. Additionally, the allocation of the decoupling capacitors could become an issue due to the increased complexity of a 3-D grid [2]. To this end, the understanding of the design parameter tradeoffs, the careful allocation of the vertical and horizontal interconnects, and decoupling capacitors can improve the overall efficiency of the Power Distribution Network (PDN) within a 3-D IC.…”

Synchronization and power integrity issues in 3-D ICs

“…A recent method to allocate metal-insulator-metal (MIM) and typical MOS capacitors in 3-D circuits is proposed in [19]. The objective of the method is to satisfy the specified voltage drop constraints, while not increasing significantly the routing congestion (due to MIM capacitors) and not exceeding the available area (due to the MOS capacitors).…”

Addressing thermal and power delivery bottlenecks in 3D circuits

“…The approach in [28] presents an approach for decap allocation in 3D power grids, using both conventional CMOS decaps and metal-insulator-metal (MIM) decaps. MIM capacitors are fabricated between metal layers, and have high capacitance density and low leakage current density.…”

“…However, they cannot be used unconditionally to replace CMOS decaps, since their use incurs a cost: they present routing blockages to nets that attempt to cross them. In [28], the decap budgeting problem, using both CMOS and MIM decaps, is formulated as a Linear Programming (LP) problem, and an efficient congestion-aware algorithm is proposed to optimize the power supply noise. An iterative flow is used to solve the decap allocation problem, based on a sequence of linear programs formulation.…”