Congestion-driven placement using a new multi-partitioning heuristic

Mayrhofer, S.; Lauther, Ulrich

doi:10.1109/iccad.1990.129917

Cited by 53 publications

(31 citation statements)

References 12 publications

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“…Therefore, estimation algorithms are required for congestion analysis during earlier phases of the design. Previous work in this area use either empirical models [1] [9] or global routers to model congestion [4][5] [8] [10]. Most empirical models need design-specific tuning, and do not correlate well to the real congestion.…”

Section: Introductionmentioning

confidence: 99%

Estimating routing congestion using probabilistic analysis

Lou

Krishnamoorthy

Sheng

2001

Proceedings of the 2001 International Symposium on Physical Design

138

180

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Design routability is a major concern in the ASIC design flow, particularly with today's increasingly aggressive process technology nodes. Increased die areas, cell densities, routing layers, and net count all contribute to complex interconnect requirements, which can significantly deteriorate performance, and sometimes lead to unroutable solutions. Congestion analysis and optimization must be performed early in the design cycle to improve routability. This paper presents a congestion estimation algorithm for a placed netlist. We propose a net-based stochastic model for computing expected horizontal and vertical track usage, which considers routing blockages. The main advantages of this algorithm are accuracy and fast runtime. We show that the congestion estimated by this algorithm correlates well with postroute congestion, and show experimental results of subsequent congestion optimization based this algorithm.

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Section: Introductionmentioning

confidence: 99%

Estimating routing congestion using probabilistic analysis

Lou

Krishnamoorthy

Sheng

2001

Proceedings of the 2001 International Symposium on Physical Design

138

180

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“…In one approach [Mayrhofer and Lauther 1990], a precomputed Steiner tree topology on a few grid structures is used for wiring-demand estimation. This approach is tailored for recursive partition-based placement.…”

Section: Topology-based Modelingmentioning

confidence: 99%

Large-scale circuit placement

Cong¹,

Shinnerl²,

Xie³

et al. 2005

ACM Trans. Des. Autom. Electron. Syst.

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Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and system performance in deep submicron technologies. The placement problem has been studied extensively in the past 30 years. However, recent studies show that existing placement solutions are surprisingly far from optimal. The first part of this tutorial summarizes results from recent optimality and scalability studies of existing placement tools. These studies show that the results of leading placement tools from both industry and academia may be up to 50% to 150% away from optimal in total wirelength. If such a gap can be closed, the corresponding performance improvement will be equivalent to several technology-generation advancements. The second part of the tutorial highlights the recent progress on large-scale circuit placement, including techniques for wirelength minimization, routability optimization, and performance optimization.

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“…Often congestion reduction is done in detailed placement or in a post-placement-optimization (see [16], [17], [18], [19], and [23]). Other authors incorporate the goal of congestion reduction into the global placement: In [10], it is shown how quadratic placement can be modified in order to avoid routing problems; in [9], the authors describe a partitioning approach that works similar to Min-Cut partitioning, but has minimization of congestion as a goal. The partitioning based algorithm in [5] increases the estimated area consumption after a global placement for cells in congested regions and then repeats the last levels of the partitioning while considering these modified cell sizes.…”

Section: Introductionmentioning

confidence: 99%

An effective congestion driven placement framework

Brenner

Rohe

2002

Proceedings of the 2002 International Symposium on Physical Design

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We present a fast but reliable way to detect routing criticalities in VLSI chips. In addition, we show how this congestion estimation can be incorporated into a partitioning based placement algorithm. Different to previous approaches, we do not rerun parts of the placement algorithm or apply a post-placement optimization, but we use our congestion estimator for a dynamic avoidance of routability problems in one single run of the placement algorithm. Computational experiments on chips with up to 1,300,000 cells are presented: The framework reduces the usage of the most critical routing edges by 9.0% on average, the running time increase for the placement is about 8.7%. However, due to the smaller congestion, the running time of routing tools can be decreased drastically, so the total time for placement and (global) routing is decreased by 47% on average.

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Congestion-driven placement using a new multi-partitioning heuristic

Cited by 53 publications

References 12 publications

Estimating routing congestion using probabilistic analysis

Estimating routing congestion using probabilistic analysis

Large-scale circuit placement

An effective congestion driven placement framework

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