Contest: a fast ATPG tool for very large combinational circuits

Mahlstedt, U.; Gruning, T.; Ozcan, C.; Daehn, Wilfried

doi:10.1109/iccad.1990.129886

Cited by 22 publications

(5 citation statements)

References 11 publications

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“…Some do not use the ISCAS benchmark networks [50,15,53,69] or do not publish the total CPU times needed for comparison [70,22,71]. Others either make no experimental comparison [16,17,61,65,31,35,52,29,13,54,39], or compare against other heuristics of their own implementation [51,71,42,43,25,33,14,57,28]. These approaches vary too many factors to give good experimental results.…”

Section: Efficiencymentioning

confidence: 99%

Combinational test generation using satisfiability

Stephan

Brayton

Sangiovanni-Vincentelli

1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

247

165

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We present a robust and efficient algorithm for combinational test generation using a reduction to satisfiability (SAT). The algorithm, TEGUS, has the following features. We choose a form for the test set characteristic equation which minimizes its size. The simplified equation is solved by an algorithm for SAT using simple, but powerful, greedy heuristics, ordering the variables using depth-first search and selecting a variable from the next unsatisfied clause at each branching point. For difficult faults the computation of global implications is iterated, which finds more implications than previous approaches and subsumes structural heuristics such as unique sensitization. Without random tests or fault simulation, TEGUS completes on every fault in the ISCAS networks, demonstrating its robustness, and is 11 times faster for those networks which have been completed by previous algorithms. Our publicly available implementation of TEGUS can be used as a base line for comparing test generation algorithms; we present comparisons with 45 recently published algorithms. TEGUS combines the advantages of the elegant organization of SAT-based algorithms, such as that by Svanaes, with the efficiency of structural algorithms, such as the D-algorithm.

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Section: Efficiencymentioning

confidence: 99%

Combinational test generation using satisfiability

Stephan

Brayton

Sangiovanni-Vincentelli

1996

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

247

165

View full text Add to dashboard Cite

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“…• 9-V [14] and 16-V [15] algebra for more precise implication process and search space reduction; • X-path check [3] for early detection of inconsistency during propagation; • unique sensitization [4] and structural dominators [5]- [7] as efficient dynamic learning techniques during propagation; • static learning [6] as an efficient technique for deriving new dependencies between signals during preprocessing; • recursive learning [16] as an efficient dynamic learning technique during propagation and justification; • single-cone processing [17] and single path-oriented propagation [8], [12] as efficient approaches for search space reduction; • backward justification [8], [18] as an alternative of forward justification making decisions only on the primary inputs [3], headlines [4], and implication nodes [19]; • Boolean satisfiability method as an elegant model of the TPG problem [1] allowing some powerful learning techniques to be used during the branch and bound search. The processes that determine the efficiency of TPG algorithms are implication, propagation, justification, fault scheduling and merging [20]- [22], and fault simulation [23].…”

Section: Introductionmentioning

confidence: 99%

SPIRIT: a highly robust combinational test generation algorithm

Gizdarski

Fujiwara

2002

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper, an efficient test pattern generation (TPG) algorithm for combinational circuits based on the Boolean satisfiability method (SAT) is presented. The authors propose a new data structure for the complete implication graph that increases the precision of implication process. Next, they examine approaches like a single-cone processing, single path-oriented propagation, and backward justification and show that they are efficient to improve robustness of TPG algorithms. Finally, the authors propose efficient techniques and heuristics for these approaches. The resultant automatic test pattern generation system, called SPIRIT (Satisfiability Problem Implementation for Redundancy Identification and Test generation), combines the flexibility of the SAT-based TPG algorithms with the efficiency of the structural TPG algorithms. Experimental results demonstrate the robustness of the proposed TPG algorithm. Without fault simulation, SPIRIT is able to achieve 100% fault efficiency for a large set of benchmark circuits in a reasonable amount of time.

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“…In a further experiment, we compare the CPU-time for test generation of our approach to those of Socrates [9], Nemesis [10], TRAN [16], CONTEST [14] and the approach of Kundu et al [22]. Table 7 Table 7 show the geometric mean of the CPU-times, an approximation of the machine speed (SPECint89), the geometric mean of CPU-times weighted with the corresponding machine speed, and the speed of the test generation normalized to the approach proposed in this paper.…”

Section: Resultsmentioning

confidence: 99%

“…Schulz et al [9] further extended Fujiwara's method by introducing an improved implication and unique sensitization procedure. Further improvements were suggested, e.g., [11,14,15], however, a directed propagation has not been achieved. Larrabee [10] and Chakradar et al [16] proposed to duplicate the part of the circuit that is in the transitive fanout of the fault location.…”

Section: Previous Approachesmentioning

confidence: 99%