Continuous time Δ Σ modulation with PWM pre-coding and binary g _m blocks

Abstract

We present a very simple technique to implement the first integrator of a continuous-time delta sigma modulator (CT-DSM). In the approach, the CT-DSM is preceded by a pulse-width modulator to convert the input signal to a pseudo-digital continuous time waveform. As a result, the first integrator of the DSM can be implemented with a capacitor and a switched current source, with inherent linearity. To illustrate the concept, it has been applied to the design of a 2nd order CT-DSM in 65nm CMOS technology. Introduction:Recently, various A/D conversion techniques that employ some kind of Pulse Width Modulation (PWM) have been presented [1,2,3]. Such a PWM converts a baseband signal into a two-level continuous time waveform. Here, the information is stored in the transitions of this 2-level waveform. If properly designed, no information is lost in this process. The two-level signal that comes out of the PWM can be easily processed by other circuit blocks. This way, a PWM is sometimes used in front of other blocks in the system's signal path. This technique is referred to as PWM pre-coding. In prior work, PWM pre-coding has been used to linearize a VCO-based ADC [1]. Alternatively, in [2] a time-to-digital converter was combined with a PWM pre-coding to convert the PWM signal into the digital domain. The former approach [1] achieves a 1st order quantization noise shaping, while the latter [2] exhibits no noise shaping at all.In this letter we present a new method for utilizing PWM pre-coding in the design of an ADC. In this work, the PWM is followed by a ContinuousTime Delta-Sigma modulator (CT-DSM) which, in contrast with previous works, can have quantization noise-shaping of any arbitrary order.

Charge pump‐ and VCO‐based second‐order delta‐sigma ADC

“…To remove the power-hungry front-end analogue integrator in high-order delta-sigma ADCs, multi-stage noise shaping (MASH) and single-loop topologies with VCO-based quantisers have been developed [3,4], leading to mostly-digital ADC architectures. In [5], a charge pump and a binary gm-c integrator are used to build the second-order deltasigma ADC. However, only single-bit quantisation is used, limiting the ADC accuracy.…”

True high‐order VCO‐based ADC

“…The second and later integrators are still in the analogue domain, but their implementation is very relaxed because their errors are reduced by the gain of preceding integrators. Moreover, particularly the second integrator has a pseudo-digital input and can be realised using a set of charge-pump integrators (switched current sources and a capacitor) [5]. Local feedbacks to create notches in the noise transfer function (NTF), as in conventional CT-DSMs, can also be integrated into this scheme.…”

“…Implementation considerations: The proposed structure has a VCO input stage and as such it is directly affected by the VCO's nonlinearity. However, there are several ways to solve this problem, including PWM pre-coding [4,5] and post calibration [6].…”