Controlled silicon thinning for design debug of C4 packaged ICs

Goruganthu, R. R.; Bruce, Mike; Birdsley, Jeff; Bruce, Victoria J.; Gilfeather, G.; Ring, Rose; Antoniou, Nicholas; Salen, Jesse A.; Thompson, M. O.

doi:10.1109/relphy.1999.761634

Cited by 6 publications

(3 citation statements)

References 2 publications

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“…Most commonly, grinding, lapping or polishing are used for the removal of the major part of the material, usually followed by a stress-relief step, where dry etching, wet etching or laser chemical etching are employed for the removal of the last 10 -100 µm of silicon, to reduce the backside damage caused by the previous coarse step and ensure a smooth surface finish ([4] - [6]). …”

Section: Introductionmentioning

confidence: 99%

“…In [4], the dicing-bythinning concept was introduced, where the depth of dicing grooves, which have been dry-etched at the front side of the wafer, defines the final silicon thickness, after the chips have been separated. In [6], the authors tried to control the thinning locally, using the signal obtained from an optical beam induced current, which varies depending on the remaining silicon.…”

Section: Introductionmentioning

confidence: 99%

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Controlled silicon IC thinning on individual die level for active implant integration using a purely mechanical process

Giagka

Saeidi

Demosthenous

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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We are developing an electrode array for epidural spinal cord stimulation and a thin integrated circuit (IC) is to be embedded in it. This paper focuses on the development and characterization of a manual process for thinning individual IC die and discusses the issues associated with thinning small dice by a manual process. The procedure allows easy and controlled post-separation thinning of small (about 1 mm 2 ) silicon chips by grinding. A systematic approach was followed to characterize the technique and repeatability of the results. With the setup we introduced we were able to control the final thickness of the IC with a standard deviation of 9.2 µm. Although no chemical processing is used, a small grit size film can create smooth surfaces, with roughness comparable to reported values after etching, acting as the socalled "stress-relief" step. Electrical tests performed on a thinned stimulator output stage IC indicated that no die damage was caused by the procedure. Some issues regarding the integration of thinned ICs on flexible substrates and the reliability of gold ball rivet bonds on the ICs' aluminium pads are also discussed.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Controlled silicon IC thinning on individual die level for active implant integration using a purely mechanical process

Giagka

Saeidi

Demosthenous

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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show abstract

“…The two methods studied in this paper are plasma etch and backside grinding and polishing. Other thinning processes exist such as laser chemical etching [8], wet chemical etch, and focused ion beam (FIB).…”

Section: Tyfjes Of Si Wafer Thinning Methodsmentioning

confidence: 99%

Enabling technologies for integrated system-on-a-package for the next generation aerospace applications

Young

Malshe

Brown³

et al.

Proceedings, IEEE Aerospace Conference

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Since the trend for electronic systems now requires more functional density not only per unit area, hut also per unit volume, and as electronic systems become smaller and thinner, the next logical step is to thin the integrated circuit (IC). This paper looks at the mechanical and morphological effects of the thinning process on the IC, and discusses thermal management schemes used to operate the t h i i e d IC at higher power levels. The methods used for thinning the chips in this study are plasma etching and mechanical polishmg. The chips were thinned to a thickness of approximately 50 -80 microns. This paper compares the effects of these two thinning processes on the chip's surface morphology and mechanical properties. In addition to the physical analysis of the chip, different thermal management schemes are also investigated in order to help increase the chip's operating power in both the flip chip and wire bond configurations. Polyimide is a desirable substrate for conformal circuitry because of its mechanical flexibility, yet it is a poor conductor of heat. Therefore, the thermal management schemes must be inteegrated into the polyimide substrate in order to increase the flow of heat away from the chips. The investigated schemes are thermal vias and micro heat channels. Finite element analysis was used to model these thermal management schemes.

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Performance improvement of Si-CCD detector based backside reflected light and photon emission microscopy by FIB ultimate substrate thinning

Glowacki¹,

Boit²,

Perdu³

2011

Microelectronics Reliability

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Controlled silicon thinning for design debug of C4 packaged ICs

Cited by 6 publications

References 2 publications

Controlled silicon IC thinning on individual die level for active implant integration using a purely mechanical process

Controlled silicon IC thinning on individual die level for active implant integration using a purely mechanical process

Enabling technologies for integrated system-on-a-package for the next generation aerospace applications

Performance improvement of Si-CCD detector based backside reflected light and photon emission microscopy by FIB ultimate substrate thinning

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