Controlling DPPM through Volume Diagnosis

Abstract

We propose to achieve and maintain ultra-high quality of digital circuits on a per-design basis by (i) monitoring the type of failures that occur through volume diagnosis, and (ii) changing the test patterns to match the current failure population characteristics. Opposed to the current approach that assumes sufficient quality levels are maintained using the tests developed during the time of design, the methodology described here presupposes that fallout characteristics can change over time but with a time constant that is sufficiently slow, thereby allowing test content to be altered so as to maximize coverage of the failure types actually occurring. Even if this assumption proves to be false, the test content can be tuned to match the characteristics of the fallout population if the fallout characteristics are unchanging. Under either scenario, it should be then possible to minimize DPPM for a given constraint on test costs, or alternatively ensure that DPPM does not exceed some pre-determined threshold. Our approach does not have to cope with situations where fallout characteristics change rapidly (e.g. excursion), since there are existing methods to deal with them. Our methodology uses a diagnosis technique that can extract defect activation conditions, a new model for estimating DPPM, and an efficient test selection method for reducing DPPM based on volume diagnosis results. Circuit-level simulation involving various types of defects shows that DPPM could be reduced by 30% using our methodology. In addition, experiments on a real silicon chip failures show that DPPM can be significantly reduced, without additional test execution cost, by altering the content (but not the size) of the applied test set.

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

“…After the defects are identified and their failure mechanisms are understood, actions can be taken to prevent their future occurrence for improving yield. In addition, more specific tests can be generated to screen for these defects to improve product quality [22,23].…”

“…The methodologies developed include evaluating the effectiveness of DFM (design-for-manufacturability) rules [24] in systematic-defect prevention, identifying and understanding systematic defects [25] to guide process improvement effort, formulate new DFM rules [26] or identify targets for test [22,27], and creating a framework for fast and accurate defect simulation [28] to validate these and other emerging test/yield learning methodologies (e.g., [29]). for the three shaded bubbles in Figure 5, which indicate the three problems addressed in this dissertation.…”

“…Diagnosis is also used as a part of a yieldmonitoring vehicle for estimating defect density and size distributions (DDSDs) [79]. In [22,23,80], diagnosis is used to monitor and control IC quality. Finally, in [81], volume-diagnosis is a key part of a methodology for evaluating test metrics and fault models without performing conventional test experiments.…”

LASIC: Layout Analysis for Systematic IC-Defect Identification Using Clustering

“…To address these issues, volume diagnosis is increasingly deployed to improve/supplement yield-learning [3][4][5][6][7][8][9][10][11][12][13][14]. Volume diagnosis refers to the process of performing software-based diagnoses of a large amount of IC test fail data, which is further analyzed for a variety of purposes.…”

“…Diagnosis is also used as a part of a yield-monitoring vehicle for estimating defect density and size distributions (DDSDs) [12]. In [13][14][15], diagnosis is used to monitor and control IC quality. Finally, in [16], volume-diagnosis is a key part of a methodology for evaluating test metrics and fault models without performing conventional test experiments.…”