Most individuals with intellectual disabilities (ID) demonstrate problems in learning and movement coordination. Consequently, they usually have difficulties in activities such as standing, walking, and stair climbing. To monitor the physical impairments of these children, regular gross motor evaluation is crucial. Straight-line level walking is the most frequently used test of their mobility. However, numerous studies have found that unless the children have multiple disabilities, no significant differences can be found between the children with ID and typically-developed children in this test. Stair climbing presents more challenges than level walking because it is associated with numerous physical factors, including lower extremity strength, cardiopulmonary endurance, vision, balance, and fear of falling. Limited ability in those factors is one of the most vital markers for children with ID. In this paper, we propose a sensor-based approach for measuring stair-walking performance, both upstairs and downstairs, for adolescents with ID. Particularly, we address the problem of sensor calibration to ensure measurement accuracy. In total, 62 participants aged 15 to 21 years, namely 32 typically-developed (TD) adolescents, 20 adolescents with ID, and 10 adolescents with multiple disabilities (MD), participated. The experimental results showed that stair-walking is more sensitive than straight-line level walking in capturing gait characteristics for adolescents with ID.

N -detect test has been shown to have a higher likelihood for detecting defects. However, traditional definitions of Ndetect test do not necessarily exploit the localized characteristics of defects. In physically-aware N-detect test, the objective is to ensure that the N tests establish N different logical states on the signal lines that are in the physical neighborhood surrounding the targeted fault site. We present a test selection procedure for creating a physicallyaware N -detect test set that satisfies a user-provided constraint on test-set size. Results produced for an industrial test chip demonstrate the effectiveness and practicability of our pattern selection approach. Specifically, we show that we can virtually detect the same number of faults 10 or more times as a traditional 10-detect test set and increase the number of neighborhood states and the number of faults with 10 or more states by 18.0 and 4.7%, respectively, without increasing the number of tests over a traditional 10-detect test set.

We propose to achieve and maintain ultra-high quality of digital circuits on a per-design basis by (i) monitoring the type of failures that occur through volume diagnosis, and (ii) changing the test patterns to match the current failure population characteristics. Opposed to the current approach that assumes sufficient quality levels are maintained using the tests developed during the time of design, the methodology described here presupposes that fallout characteristics can change over time but with a time constant that is sufficiently slow, thereby allowing test content to be altered so as to maximize coverage of the failure types actually occurring. Even if this assumption proves to be false, the test content can be tuned to match the characteristics of the fallout population if the fallout characteristics are unchanging. Under either scenario, it should be then possible to minimize DPPM for a given constraint on test costs, or alternatively ensure that DPPM does not exceed some pre-determined threshold. Our approach does not have to cope with situations where fallout characteristics change rapidly (e.g. excursion), since there are existing methods to deal with them. Our methodology uses a diagnosis technique that can extract defect activation conditions, a new model for estimating DPPM, and an efficient test selection method for reducing DPPM based on volume diagnosis results. Circuit-level simulation involving various types of defects shows that DPPM could be reduced by 30% using our methodology. In addition, experiments on a real silicon chip failures show that DPPM can be significantly reduced, without additional test execution cost, by altering the content (but not the size) of the applied test set.

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