Physically-Aware N-Detect Test Pattern Selection

Lin, Yen-Tzu; Poku, Osei; Bhatti, Naresh K.; Blanton, R. D.

doi:10.1109/date.2008.4484748

Cited by 16 publications

(12 citation statements)

References 15 publications

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“…Note that, by using two weights wo(i,0) and wo(i,1) for each output i we enforce the selection of test vectors which provide high deviation values for both fault free responses 0 and 1 at this output since we control the number of vectors which provide high deviation value for each response separately. We verified experimentally that a value of F 2 in the range [2,10] is sufficient to guarantee the selection of test vectors which provide high deviation values at all outputs. We have chosen the value of F 2 = 8 in the experiments reported in Section 4.…”

Section: Proposed Test-generation Methodsmentioning

confidence: 78%

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Generation of compact test sets with high defect coverage

Kavousianos

Chakrabarty

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Multi-detect (N-detect) testing suffers from the drawback that its test length grows linearly with N. We present a new method to generate compact test sets that provide high defect coverage. The proposed technique makes judicious use of a new pattern-quality metric based on the concept of output deviations. We select the most effective patterns from a large N-detect pattern repository, and guarantee a small test set as well as complete stuck-at coverage. Simulation results for benchmark circuits show that with a compact, 1-detect stuck-at test set, the proposed method provides considerably higher transition-fault coverage and coverage ramp-up compared to another recently-published method. Moreover, in all cases, the proposed method either outperforms or is as effective as the competing approach in terms of bridging-fault coverage and the surrogate BCE+ metric. In many cases, higher transition-fault coverage is obtained than much larger N-detect test sets for several values of N. Finally, our results provide the insight that, instead of using N-detect testing with as large N as possible, it is more efficient to combine the output deviations metric with multi-detect testing to get highquality, compact test sets.

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Section: Proposed Test-generation Methodsmentioning

confidence: 78%

“…This method was proposed in [11], and since then it has been identified as a very effective test strategy [1]- [6], [8]- [10], [13]- [17]. The main idea of N-detect testing is to apply N (N > 1) different test patterns for each stuck-at fault.…”

Section: Introduction *mentioning

confidence: 99%

Generation of compact test sets with high defect coverage

Kavousianos

Chakrabarty

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…The methodologies developed include evaluating the effectiveness of DFM (design-for-manufacturability) rules [24] in systematic-defect prevention, identifying and understanding systematic defects [25] to guide process improvement effort, formulate new DFM rules [26] or identify targets for test [22,27], and creating a framework for fast and accurate defect simulation [28] to validate these and other emerging test/yield learning methodologies (e.g., [29]). for the three shaded bubbles in Figure 5, which indicate the three problems addressed in this dissertation.…”

Section: This Is Illustrated Inmentioning

confidence: 99%

“…Tests generated using a given fault model can be simulated with SLIDER to evaluate its effectiveness in defect detection. Tests generated using a given test metric (e.g., physically-aware N-detect [29]) can be subject to the same analysis to evaluate the effectiveness of the test metric.…”

Section: Framework Usagementioning

confidence: 99%

“…Virtual failure data are useful for validating and debugging any method that requires test-measurement data from failing ICs. For example, a test metric (e.g., physically-aware N-detect [29]) can be evaluated to determine its effectiveness in generating tests to detect defects. Similarly, as shown in Section 4.4.3, a diagnosis technique can also be evaluated to determine its accuracy in identifying the defect location.…”

Section: Slider Contributionsmentioning

confidence: 99%

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Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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In the integrated circuit (IC) industry, all products must go through three phases before they are available in the market, namely design, manufacturing, and testing. Design, obviously, refers to the process of converting the early concepts of the product into a precise description of its implementation. Manufacturing then uses this description to fabricate the product, where the design is physically materialized onto the silicon wafer and later packaged into the product. If design and manufacturing are perfect, then every fabricated IC is completely functional, thereby obliterating the need for testing. Unfortunately, both design and manufacturing are not ideal; therefore every manufactured IC must be subject to stringent testing procedures to ensure that most bad ICs are identified and prevented from shipping to the end-users.ICs are deemed bad when they contain certain defects that cause the ICs to fail the specifications.Defects are unintended structural and/or material changes of the IC due to design/manufacturing imperfections.These physical changes may alter the electrical characteristics of the circuit, which are sometimes severe enough to lead to a failure (i.e., violation of one or more design specifications). Common defects in IC manufacturing can be caused by contaminations in the process, variations of the process conditions, or simply the difficulty to fabricate certain features of the design. The last issue is the focus of this dissertation. Defects that arise due to certain aspects of the design being sensitive to the manufacturing process with an elevated likelihood of failure are known as systematic defects. This dissertation addresses the issues related to the prevention and identification of systematic defects by analyzing a large amount of manufactured ICs that have failed testing.For systematic-defect prevention, one common approach is to use design-for-manufacturability (DFM) rules to communicate hard-to-manufacture features to designers so that these features can be minimized in the iii design. Obviously, different rules describe different features and thus their violation/adherence will have different impact on the manufacturability of the product. It is therefore desirable to measure the relative importance of the rules and how they affect product yield. To address this issue, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of DFM rules in preventing systematic defects. RADAR analyzes a large amount of test data of failed ICs to draw statistical conclusion.Taking preventive measures, such as enforcing DFM rules, is necessary to ensure sufficient product yield. Unfortunately, the amount of resource (circuit area, designer's time, etc.) dedicated to DFM can be quite limited. It is therefore impractical to anticipate and prevent every possible hard-to-manufacture design features before the product is manufactured. Thus, systematic defects can still exist. Therefore, a mechanism is required to identify systematic ...

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Efficient testing of multi‐output combinational cells in nano‐complementary metal oxide semiconductor integrated circuits

Valenti

Dalpasso²,

Favalli

2014

IET Computers & Digital Techniques

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This study addresses the problem of efficient fault simulation and test generation in circuits using multi-output combinational logic cells. A symbolic fault simulation algorithm is proposed to exploit bit-level parallelism in order to represent the propagation of the output value of faulty cells throughout the circuit, thus accounting for different faulty behaviours in a single simulation step. A satisfiability (SAT)-based test generation procedure is also provided and it early discovers sets of undetectable behaviours. Results for a set of combinational benchmarks show the feasibility of the proposed approach

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Physically-Aware N-Detect Test Pattern Selection

Cited by 16 publications

References 15 publications

Generation of compact test sets with high defect coverage

Generation of compact test sets with high defect coverage

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Efficient testing of multi‐output combinational cells in nano‐complementary metal oxide semiconductor integrated circuits

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