2009 International Conference on Simulation of Semiconductor Processes and Devices 2009
DOI: 10.1109/sispad.2009.5290254
|View full text |Cite
|
Sign up to set email alerts
|

Convex Channel Design for Improved Capacitorless DRAM Retention Time

Abstract: Abstract-A convex channel surface with Si 0.8 Ge 0.2 is proposed to enhance the retention time of a capacitorless DRAM Generation 2 type of capacitorless DRAM cell. This structure provides a physical well together with an electrostatic barrier to more effectively store holes and thereby achieve larger sensing margin as well as retention time. The advantages of this new cell design as compared with the planar cell design are assessed via twodimensional device simulations. The results indicate that the convex he… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2011
2011
2015
2015

Publication Types

Select...
3
2
1

Relationship

0
6

Authors

Journals

citations
Cited by 9 publications
(1 citation statement)
references
References 7 publications
0
1
0
Order By: Relevance
“…A convex channel 1T-DRAM structure (Fig. 11a) using the BJT programming technique was proposed to improve the retention time in [32]. The holes are stored beneath a raised gate oxide which may be filled by a smaller bandgap material (e.g.…”
Section: Electron-hole Separationmentioning
confidence: 99%
“…A convex channel 1T-DRAM structure (Fig. 11a) using the BJT programming technique was proposed to improve the retention time in [32]. The holes are stored beneath a raised gate oxide which may be filled by a smaller bandgap material (e.g.…”
Section: Electron-hole Separationmentioning
confidence: 99%