Abstract-The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22 nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are analyzed for FD-SOI versus bulk SRAM cells. Iso-area and iso-yield comparisons are then made to determine the yield and cell-area benefits of FD-SOI technology, respectively. Finally, the minimum operating voltages (V min ) required for FD-SOI and bulk SRAM cells to meet the six-sigma yield requirement are compared.

The performance and yield of 6-T SRAM cells implemented in thin-BOX FD-SOI technology vs. bulk technology are compared via 3-dimensional (3D) atomistic process and device simulations and analytical modeling for SRAM yield estimation. Performance is enhanced due to the elimination of channel dopants, and variation due to gate-LER and RDF are suppressed, for FD-SOI technology. For the same cell area (~0.07μm 2 ), comparable SNM can be achieved with 30% higher write current, and SRAM yield is enhanced by >2 sigma. IntroductionContinued bulk MOSFET and SRAM cell area scaling are becoming increasingly difficult due to increased random variation in transistor performance with decreasing gate length (L GATE ), caused by gate line-edge roughness (LER) and random dopant fluctuations (RDF) [1]. The use of a lightly doped (fully depleted) SOI MOSFET structure with a thin (~10 nm-thick) buried oxide (BOX) and a heavily doped substrate has been reported to be effective for suppressing this variation [2]. The thin-BOX structure (vs. a thick-BOX structure) has been shown to be optimal for SRAM in sub-50nm technology nodes [3]. In this work, the benefits of thin-BOX FD-SOI technology vs. bulk MOSFET technology for improving 6-T SRAM cell yield at the 22nm technology node are assessed, via 3-dimensional (3D) atomistic process and device simulations and analytical modeling for SRAM yield estimation.

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Abstract-A convex channel surface with Si 0.8 Ge 0.2 is proposed to enhance the retention time of a capacitorless DRAM Generation 2 type of capacitorless DRAM cell. This structure provides a physical well together with an electrostatic barrier to more effectively store holes and thereby achieve larger sensing margin as well as retention time. The advantages of this new cell design as compared with the planar cell design are assessed via twodimensional device simulations. The results indicate that the convex heterojunction channel design is very promising for future capacitorless DRAM.

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