Variation Study and Implications for BJT-Based Thin-Body Capacitorless DRAM

Cho, Min Hee; Liu, Tsu‐Jae King

doi:10.1109/led.2011.2179002

Cited by 4 publications

(2 citation statements)

References 9 publications

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“…Therefore, the refresh time of an array of DRAMs, which is determined by the DRAM cells that are more susceptible to variations such as RDF, increases. For a Silicon-on-Insulator-based 1T DRAM, the critical parameters contributing to the variability are silicon film thickness, thickness of the buried oxide and RDF [18]. These variations can reduce the RT in a DRAM by 63% for the 22 − nm technology node.…”

Section: Introductionmentioning

confidence: 99%

Dopingless 1T DRAM: Proposal, Design, and Analysis

James

Saurabh

2019

IEEE Access

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In this paper, we have proposed a dopingless 1T DRAM (DL-DRAM) that utilizes the charge plasma concept. The proposed device employs a misaligned double-gate architecture to store holes and differentiates between the two logic states. The source, drain, backgate, and frontgate workfunctions are optimized to achieve the required concentration profiles in an intrinsic silicon body. Using TCAD simulations, we have analyzed the read/write mechanism in the device. Our study shows that the mechanism of current transport during reading operation depends strongly on the source workfunction. When the source workfunction is less than 4.5 eV the transport mechanism during reading is dominated by driftdiffusion. However, when the source workfunction is greater than 4.5 eV , the transport mechanism during read is dominated by band-to-band tunneling (BTBT). In general, when the dominant mechanism of current transport is BTBT, the retention time and the read-1/0 current ratio is higher, and the sense margin is lower in the case in which the dominant mechanism of current transport is drift-diffusion. Due to the avoidance of doping, the proposed DL-DRAM is expected to be free from random dopant fluctuation. Moreover, high temperature annealing processes required after ion implantation can be avoided. The lower thermal requirements of a DL-DRAM opens the possibility of fabricating DRAMs using processes which are compatible with bio-materials and opto-electronics and in ensuring bottom MOSFET and interconnects preservation in 3D VLSI integration. INDEX TERMS DRAM, dopingless, sense margin, retention time, charge plasma.

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Section: Introductionmentioning

confidence: 99%

Dopingless 1T DRAM: Proposal, Design, and Analysis

James

Saurabh

2019

IEEE Access

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“…[10][11][12][13][14][15][16] This is a limitation in scaling down gate length and floating body thickness, because retention properties of floating body effects suffer from short channel effects such as draininduced barrier lowering (DIBL) but PDSOI structure cannot effectively suppress these problems, which results in low-grade retention characteristics of volatile memory function. [17][18][19][20][21][22][23][24][25][26] In this work, a single memory cell having both volatile and non-volatile functions is demonstrated with an independent asymmetric dual-gate and a thin, fully depleted body structure. The volatile memory (VM) can be obtained even in a fully depleted body thanks to the field effect of trapped charges in the nitride layer and the nitride layer allows the non-volatile memory (NVM) in the device at the same time.…”

Section: Introductionmentioning

confidence: 99%

Combination of volatile and non-volatile functions in a single memory cell and its scalability

Kim¹,

Hwang²,

Lee³

et al. 2017

Jpn. J. Appl. Phys.

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A single memory cell which combines volatile memory and non-volatile memory functions has been demonstrated with an independent asymmetric dual-gate structure. Owing to the second gate whose dielectric is composed of oxide/nitride/oxide layers, floating body effect was observed even on a fully depleted silicon-on-insulator device and the non-volatile memory function was measured. In addition, read retention characteristics of the volatile memory function depending on the non-volatile memory state were evaluated and analyzed. Further scalability in body thickness was also verified through simulation studies. These results indicate that the proposed device is a promising candidate for high-density embedded memory applications.

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Addressing key challenges in 1T-DRAM: Retention time, scaling and variability — Using a novel design with GaP source-drain

Pal

Nainani

Saraswat

2013

2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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Variation Study and Implications for BJT-Based Thin-Body Capacitorless DRAM

Cited by 4 publications

References 9 publications

Dopingless 1T DRAM: Proposal, Design, and Analysis

Dopingless 1T DRAM: Proposal, Design, and Analysis

Combination of volatile and non-volatile functions in a single memory cell and its scalability

Addressing key challenges in 1T-DRAM: Retention time, scaling and variability — Using a novel design with GaP source-drain

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Variation Study and Implications for BJT-Based Thin-Body Capacitorless DRAM

Cited by 4 publications

References 9 publications

Dopingless 1T DRAM: Proposal, Design, and Analysis

Dopingless 1T DRAM: Proposal, Design, and Analysis

Combination of volatile and non-volatile functions in a single memory cell and its scalability

Addressing key challenges in 1T-DRAM: Retention time, scaling and variability &#x2014; Using a novel design with GaP source-drain

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Product

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Addressing key challenges in 1T-DRAM: Retention time, scaling and variability — Using a novel design with GaP source-drain