SRAM cell design considerations for SOI technology

Liu, Tsu‐Jae King; Shin, Changhwan; Cho, Min Hee; Sun, Xun; Nikolić, Borivoje; Nguyen, Bich‐Yen

doi:10.1109/soi.2009.5318784

Cited by 5 publications

(1 citation statement)

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“…1 shows a cross-sectional schematic diagram of the UTB FDSOI device. Design parameters were chosen according to [12] for good SCE control and are summarized in Table 1. Devices with and without heavily doped Ground Planes (GP) beneath the Buried Oxide (BOX) layer are considered.…”

Section: Device Structure Descriptionmentioning

confidence: 99%

Neutron-induced single-event-transient effects in ultrathin-body fully-depleted silicon-on-insulator MOSFETs

Reed

Schrimpf

et al. 2013

2013 IEEE International Reliability Physics Symposium (IRPS)

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The neutron-induced single-event-transient (SET) response of 22-nm technology ultrathin-body fully-depleted silicon-on-insulator transistors is examined. Simulation resultsshow that the impacts of ground plane doping and quantum effects on SETs are relatively small. The SET characteristics and collected charge are strike-location sensitive. The most SETsensitive region in ultrathin-body fully-depleted SOI transistors is located near the drain region. The transient current peak is strongly affected by substrate bias. In contrast, the total collected charge depends only weakly on substrate bias. Circuits that are sensitive to total collected charge (e.g., SRAMs) may not be influenced by substrate bias, but substrate bias will impact the SET sensitivity of combinational logic.

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Section: Device Structure Descriptionmentioning

confidence: 99%