SRAM design in fully-depleted SOI technology

Impact of Trap Position on Random Telegraph Noise in a 70-Å Nanowire Field-Effect Transistor

“…As the critical dimensions shrink to a few nanometers, non-conventional device structures that can successfully suppress the short channel effect have been proposed. For example, doublegate FinFET [1,2], Fully-Depleted Silicon-on-Insulator (FD-SOI) MOSFET [3,4], and gate-all-around (GAA) MOSFET [5][6][7][8][9][10] have attracted much attention in the industry. Among them, the nanowire FET has the highest gate-to-channel capacitive coupling primarily because the channel is surrounded and controlled by the gate in all directions, and therefore, silicon nanowire architecture is the most attractive structure for sub-10-nm CMOS technology.…”