Convolution operation implemented in FPGA structures for real-time image processing

Jamro, E.; Wiatr, K.

doi:10.1109/ispa.2001.938666

Cited by 9 publications

(8 citation statements)

References 7 publications

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“…We applied the proposed flow on different case studies, of which we discuss the most significant two for the sake of illustration: an iterative gaussian filter [13] and the Chambolle algorithm [18]. The two algorithms are characterized by data dependencies of different complexities.…”

Section: Resultsmentioning

confidence: 99%

“…The number of iterations can either be known in advance (as, for instance, in an iterative convolution filter [13], where the amount blur corresponds to a number of filtering steps), or potentially unbounded (as in fixed point algorithms, where one would ideally iterate until an equilibrium is reached). Without loss of generality, we assume that the number of iterations is known a priori, and hence we formally define a generic ISL algorithm with the following pseudo-code:…”

Section: Iterative Stencil Loopsmentioning

confidence: 99%

“….N (number of iterations)} do for p in f i+1 do p=t p ( f i ) (t p is the function that computes only the element p of the target frame) end for end for Many algorithms for multimedia processing follow the pattern presented in Algorithm 1, such as the ones presented in [13,14,15,16,18] and [3], as well as algorithms for scientific computation, such as convolution and the Jacobi iterative algorithm to solve linear eigenvalue problems [17].…”

Section: Iterative Stencil Loopsmentioning

confidence: 99%

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A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

Nacci

Rana

Bruschi

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic design flow to extract parallelism from an ISL algorithm and perform a design space exploration to identify its best FPGA hardware implementation, in terms of both area and throughput. Experimental results show that the proposed methodology generates hardware designs whose performance is comparable to the one of manuallyoptimized solutions, and orders of magnitude higher than the implementations generated by commercial high-level synthesis tools.

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Section: Resultsmentioning

confidence: 99%

Section: Iterative Stencil Loopsmentioning

confidence: 99%

Section: Iterative Stencil Loopsmentioning

confidence: 99%

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A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

Nacci

Rana

Bruschi

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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“…Furthermore, in certain domains, such as multimedia processing, these specialized cores perform tasks that are sufficiently general to guarantee a good reusability in a wide range of systems. For example, specialized cores can be used to accelerate common operations such as convolution filters [Jamro and Wiatr 2001] or the Jacobi operator [Sleijpen and Vorst 2000].…”

Section: Introductionmentioning

confidence: 99%

Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices

Beretta

Rana

Akın

et al. 2016

ACM Trans. Embed. Comput. Syst.

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The performance and the efficiency of recent computing platforms have been deeply influenced by the widespread adoption of hardware accelerators, such as graphics processing units (GPUs) or fieldprogrammable gate arrays (FPGAs), which are often employed to support the tasks of general-purpose processors (GPPs). One of the main advantages of these accelerators over their sequential counterparts (GPPs) is their ability to perform massive parallel computation. However, to exploit this competitive edge, it is necessary to extract the parallelism from the target algorithm to be executed, which generally is a very challenging task.This concept is demonstrated, for instance, by the poor performance achieved on relevant multimedia algorithms, such as Chambolle, which is a well-known algorithm employed for the optical flow estimation. The implementations of this algorithm that can be found in the state of the art are generally based on GPUs but barely improve the performance that can be obtained with a powerful GPP. In this article, we propose a novel approach to extract the parallelism from computation-intensive multimedia algorithms, which includes an analysis of their dependency schema and an assessment of their data reuse. We then perform a thorough analysis of the Chambolle algorithm, providing a formal proof of its inner data dependencies and locality properties. Then, we exploit the considerations drawn from this analysis by proposing an architectural template that takes advantage of the fine-grained parallelism of FPGA devices. Moreover, since the proposed template can be instantiated with different parameters, we also propose a design metric, the expansion rate, to help the designer in the estimation of the efficiency and performance of the different instances, making it possible to select the right one before the implementation phase. We finally show, by means of experimental results, how the proposed analysis and parallelization approach leads to the design of efficient and highperformance FPGA-based implementations that are orders of magnitude faster than the state-of-the-art ones.

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“…Substantially faster (8 to 800 times faster) image processing in FPGA than on a PC is documented in [3]. Convolution operation implemented in FPGA to be applied for real-time image processing is given in [4]. It has also been proposed to evolve image filters in reconfigurable logic [8].…”

Section: Introductionmentioning

confidence: 99%

Efficient image filtering and information reduction in reconfigurable logic

Tørresen¹,

Bakke²,

Sekanina³

Proceedings Norchip Conference, 2004.

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An automatic sign detection system could be important in enhancing traffic safety. Such a system would have to be able to provide high speed processing in its real-time environment. In this paper, we show how one of the time consuming parts of a speed limit detection algorithm can be implemented in reconfigurable logic to speed up the processing. Results indicate that the present system would be able to handle 12 images per second.

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Convolution operation implemented in FPGA structures for real-time image processing

Cited by 9 publications

References 7 publications

A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

A high-level synthesis flow for the implementation of iterative stencil loop algorithms on FPGA devices

Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices

Efficient image filtering and information reduction in reconfigurable logic

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