Copper pillar bump technology progress overview

Koh, Wei; Lin, Barry; Tai, Johnson

doi:10.1109/icept.2011.6067027

Cited by 36 publications

(21 citation statements)

References 6 publications

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“…At higher bit rates up to 40Gb/s, solder bump technology impose restrictions due to the parasitic effects induced. In this case copper pillar technology would be more preferable [11]. In comparison with solder bumps that collapse during solder reflow, copper pillars retain their shape thus providing higher reliability, improved electrical and thermal performance as well as reduction or elimination of the lead.…”

Section: Small Signal Analysismentioning

confidence: 97%

Demonstration of a Hybrid Opto-Electronic Transmitter on SoI for Access Networks

Stamatiadis¹,

Mekonnen²,

Winzer

et al. 2014

IEEE Photon. Technol. Lett.

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We present a hybrid integrated transmitter comprised of an InP/InGaAsP electro-absorption modulated laser (EML) electrically driven by a BiCMOS SiGe electronic circuit on 4-µm SoI substrate. The EML includes an electro-absorption modulator integrated together with a distributed feedback laser and a spot-size expander. The modulator driver is fabricated using the SiGe BiCMOS approach with 2.5 V p-p nominal output swing. Both elements have been flip-chip mounted on a thick SoI board using 14-µm gold-tin bumps and employing a high accuracy flip-chip bonder. The photonic chip has a footprint of 7 mm 2 and consumes a power of 0.8 W. We test the device optically and electrically demonstrating error-free operation at 10 and 20 Gb/s. Index Terms-Hybrid photonic integration, silicon-oninsulator, opto-electronic devices, optical access, fiber to the home (FTTH).

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Section: Small Signal Analysismentioning

confidence: 97%

Demonstration of a Hybrid Opto-Electronic Transmitter on SoI for Access Networks

Stamatiadis¹,

Mekonnen²,

Winzer

et al. 2014

IEEE Photon. Technol. Lett.

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“…The power loops span the entire array connecting to C4 bumps placed symmetrically at the periphery of the array. A spacing of s C4 = 150 µm and diameter of d C4 = 75 µm is assumed for the bumps, satisfying the minimum size requirements for C4 pads placement [15]. The surrounding C4 bumps are assumed to supply the total current drawn by the array of inductors at nominal V dd = 1.1 V .…”

Section: Noise Effects Of Inductive Link Arraysmentioning

confidence: 99%

Crosstalk noise effects of on-chip inductive links on power delivery networks

Papistas

Pavlidis

2016

2016 IEEE International Symposium on Circuits and Systems (ISCAS)

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Inductive links have been proposed as an intertier interconnect solution for three-dimensional (3-D) integrated systems. Combined with signal multiplexing, inductive links achieve high communication bandwidth comparable to that of through silicon vias. However, being a wireless medium, electromagnetic coupling between the inductive link and nearby on-chip interconnects can cause voltage fluctuations affecting interconnect performance. The interference of interconnects on the operation of inductive links has been empirically investigated. Nevertheless, the reverse problem has yet to be explored. Consequently, this paper investigates the effect of electromagnetic coupling on global interconnects of the power delivery network in the vicinity of on-chip inductors. Analysis shows that operation at 6 GHz leads to an induced noise of 39.5 mV per link, which increases further if the interconnect length spans several inductors. As this noise adds to the existing power supply noise, this paper proposes amendments to the placement of the power/ground lines to maintain the power supply noise below a specified limit.

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“…The power loops span the entire array connecting to C4 bumps placed symmetrically at the periphery of the array. A spacing of sC4 = 150 µm and diameter of dC4 = 75 µm are assumed for the bumps, satisfying the minimum size requirements for C4 pad placement [17]. The surrounding C4 bumps are assumed to supply the total current drawn by the array of inductors at nominal V dd = 1.1 V .…”

Section: Induced Noise By Inductive Link Arraysmentioning

confidence: 99%

Inter-Tier Crosstalk Noise On Power Delivery Networks For 3-D ICs With Inductively-Coupled Interconnects

Papistas

Pavlidis

2016

Proceedings of the 26th Edition on Great Lakes Symposium on VLSI

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Inductive links have been proposed as an inter-tier interconnect solution for three-dimensional (3-D) integrated systems. Combined with signal multiplexing, inductive links achieve high communication bandwidth comparable to that of through silicon vias. However, being a wireless medium, electromagnetic coupling between the inductive link and nearby on-chip interconnects can cause voltage fluctuations affecting interconnect performance. Although the interference of interconnects on the operation of inductive links has been investigated, the inverse problem has yet to be explored. Consequently, this paper performs an investigation on the effect of electromagnetic coupling on different topologies of power delivery networks (PDNs) in the vicinity of on-chip inductors. Results indicate that the interdigitated PDN topology suffers from the induced noise due to the inductive links of the neighbouring tiers exhibiting a minimum aggregate noise of 131.3 mV. Alternatively, the paired topologies exhibit a superior noise behaviour, achieving a 39.4% and 35.4% decrease in noise level for paired type I and paired type II topologies, respectively, compared to the interdigitated topology.

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Copper pillar bump technology progress overview

Cited by 36 publications

References 6 publications

Demonstration of a Hybrid Opto-Electronic Transmitter on SoI for Access Networks

Demonstration of a Hybrid Opto-Electronic Transmitter on SoI for Access Networks

Crosstalk noise effects of on-chip inductive links on power delivery networks

Inter-Tier Crosstalk Noise On Power Delivery Networks For 3-D ICs With Inductively-Coupled Interconnects

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