Correcting lithography hot spots during physical-design implementation

Abstract

As the technology node shrinks, printed-wafer shapes show progressively less similarity to the design-layout shapes, even with optical proximity correction (OPC). Design tools have a restricted ability to address this shape infidelity. Their understanding of lithography effects is limited, taking the form of design rules that try to prevent "Hot Spots" -locations that demonstrate wafer-printing problems. These design rules are becoming increasingly complex and therefore less useful in addressing the lithography challenges. Therefore, design tools that have a better understanding of lithography are becoming a necessity for technology nodes of 65 nm and below. The general goal of this work is to correct lithography Hot Spots during physical-design implementation. The specific goal is to automatically fix a majority of the Hot Spots in the Metal 2 layers and above, with a run time on the order of a few hours per layer. Three steps were taken to achieve this goal. First, Hot Spot detection was made faster by using rule-based detection. Second, Hot Spot correction was automated by using rule-based correction. Third, convergence of corrections was avoided by performing correction locally, which means that correcting one Hot Spot was very unlikely to create new Hot Spots.

Lithography friendly routing: From construct-by-correction to correct-by-construction

“…Significant efforts for hotspot detection have been reported. In the rule-based approaches, a set of rules made from fab data are applied to layout [25], [28] in the form of 1D geometric measurements such as minimum line width, minimum space, forbidden pitches, and so on. However, while aggressive RET and OPC models are well defined for simple 1D geometry rules, complex interactions of 2D geometries are difficult to capture and analyze [29].…”

“…However, one has to be very conscious about the runtime as the lithography simulators could take prohibitive CPU [4]. In terms of which routing stage to apply lithography correction, there are two main paradigms, i.e., construct-by-correction [4], [5], [25] and correct-by-construction [1], [3], [26], [27]. In the construct-by-correction paradigm, the design is first routed as usual, then the litho-hotspots are detected (e.g., by some rules of thumbs or lithography simulations/models) and fixed as a post-routing optimization.…”

Nanoscale Phase Change Material Array by Sub-Resolution Assist Feature for Storage Class Memory Application

“…There is a remarkable discrepancy, which increases as the critical dimension decreases, between the patternings designed in the mask and fabricated on the wafer due to the diffraction-limited property of the lithographic imaging systems [ 18 ]. Various resolution enhancement techniques are presented to reduce the OPE and improve the quality and stability of the lithographic patterning.…”