Correlation-aware statistical timing analysis with non-gaussian delay distributions

Abstract

Process variations have a growing impact on circuit performance for today's integrated circuit (IC) technologies. The Non-Gaussian delay distributions as well as the correlations among delays make statistical timing analysis more challenging than ever. In this paper, we present an efficient block-based statistical timing analysis approach with linear complexity with respect to the circuit size, which can accurately predict Non-Gaussian delay distributions from realistic nonlinear gate and interconnect delay models. This approach accounts for all correlations, from manufacturing process dependence, to re-convergent circuit paths to produce more accurate statistical timing predictions. With this approach, circuit designers can have increased confidence in the variation estimates, at a low additional computation cost.

Quadratic Statistical $MAX$ Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits

“…Once the quadratic function MAX(0, z) is determined, it can be substituted into (18) to calculate the quadratic model for MAX(x, y). It should be noted that our moment matching in (21)- (23) is substantially different from the algorithm proposed in [23]. Zhan et al [23] attempt to match the moments for all random variables {ε i ; i = 1, 2, .…”

“…Substituting (56) into (45)-(47) yields (57)-(59). Note that the optimality conditions in (57)-(59) are exactly equivalent to the moment matching equations in (21)- (23). Therefore, the moment matching in (21)- (23) yields the optimal σ 2 , σ 1 , and σ 0 that minimize the weighted squared error in (28).…”

Variability and Statistical Design

“…A key property of this diagonalization is that it preserves the orthogonality of the principal components. This work was subsequently extended 102) to develop a clever set of manipulations to compute the result of the max operator.…”

An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis

“…Furthermore, these variations are increasing with each new generation of technology. Statistical Static Timing Analysis (SSTA) has been proposed to perform full-chip analysis of timing under such types of uncertainty, and has been the subject of intense research recently [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18]. The result of SSTA is the prediction of parametric yield at a given target performance for a design.…”

“…The original parameterized delay form expressed delays and arrival times as explicit linear functions of the process parameters [5]. It was later expanded to handle quadratic delay models that are able to improve the accuracy of delay estimates [12][13][14][15]. A related source of error, namely the modeling and handling of the slope of signals, has not received as much attention.…”