Correlation of charge transport to intrinsic strain in silicon oxynitride and Si-rich silicon nitride thin films

Habermehl, S.; Apodaca, Roger

doi:10.1063/1.1639132

Cited by 17 publications

(8 citation statements)

References 24 publications

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“…It was reported that trap level in nitride films was drastically decreased with increasing the amount of excess silicon. 5) In our case, the energy levels of the traps of Si 3 N 4 and SRN (x ¼ 0:02) obtained from the temperature dependences of the P-F plots are 1.4 and 0.8 eV, respectively, which agree well with the reported values. Accordingly, the nitrogen concentration dependence of P-F current is mainly due to the change in the trap level.…”

Section: Resultssupporting

confidence: 90%

Electron Trap Characteristics of Silicon Rich Silicon Nitride Thin Films

Mine

Fujisaki

Ishida

et al. 2007

jjap

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Charge localization causes initial retention loss and memory window narrowing after write/erase cycling in a nonvolatile memory device using a metal–oxide–nitride–oxide–semiconductor (MONOS) structure. To overcome these problems, we propose the use of silicon-rich silicon nitride (SRN) thin film as a charge-trapping layer. It was found that most of the electrons injected from the substrate were trapped at the interface between the SRN film and the top oxide and the number of electrons captured by bulk traps of the nitride is negligible. When negative bias is applied to the gate electrode, the electrons trapped at the top interface move back to the bottom interface with SRN. The high effective mobility of the electrons is presumably due to donor-like traps at 0.8 eV below the conduction band bottom of SRN.

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Section: Resultssupporting

confidence: 90%

Electron Trap Characteristics of Silicon Rich Silicon Nitride Thin Films

Mine

Fujisaki

Ishida

et al. 2007

jjap

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“…From the slope of the best straight line fit through the data in Fig. 8(b) and (d), the conduction bulk trap depth can be calculated to be 1.02 and 1.18 eV, respectively for samples A and B, which are very close to values of some other reports [33,34,[38][39][40]. A Poole-Frenkel conduction bulk trap depth of 0.809 eV was reported in the as-grown stoichiometric SiN x by LPCVD at 780 8C [41].…”

Section: Methodssupporting

confidence: 85%

Effect of alloying temperature on the capacitance–voltage and current–voltage characteristics of low‐pressure chemical vapor deposition SiN_x/n‐GaN MIS structures

Liu

Wang

et al. 2015

Physica Status Solidi (a)

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The first three authors contributed equally to this work.The low-pressure chemical vapor deposition (LPCVD)-SiN x layer is deposited prior to the ohmic alloying as the passivation layer and gate dielectric layer in GaN device fabrication. The effect of alloying temperature on the LPCVD-SiN x /GaN interface and LPCVD-SiN x dielectric film is evaluated by the capacitance-voltage (C-V) and current-voltage (I-V) characteristics. The C-V analysis by frequency-dependent method and Terman method shows that the higher density of interface states occurs at the higher alloying temperature, while I-V analysis indicates that the higher alloying temperature can lead to smaller current density with slightly deeper traps for PooleFrenkel conduction. The hydrogen-related bonds may be the cause and affects the interfacial properties of LPCVD-SiN x / GaN as well as the electrical properties of LPCVD-SiN x film.

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“…6 The barrier lowering energy at the point of breakdown ␤E BD 1/2 is independently determined from measurements of the breakdown field E BD and the optical dielectric constant ⑀ r , where ␤ = ͑q 3 / r 0 ͒ 1/2 . 7 It is noted that the current-voltage characteristics of samples investigated herein exhibit no cycling hysteresis associated with current stressing, implying that additional charge traps are not generated by the tests themselves.…”

mentioning

confidence: 74%