Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs

Chen, Chen-An; Chen, Yee-Wen; Hsu, Chun-Lung; Wu, Ming-Hsueh; Luo, Kun-Lun; Bai, Bing-Chuan; Cheng, Liang-Chia

doi:10.1109/ats.2013.29

Cited by 2 publications

(2 citation statements)

References 3 publications

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“…In that case, test stimuli need to be transported through other dies in the stack up to the die where they are meant to execute their defect detection work; likewise, test responses need to be transported from the die-under-test through other dies in the stack down to the external stack I/Os. Several ad-hoc 3D-DfT architectures have been proposed [12][13][14][15][16][17][18]; these architectures do their job, but are not fully compatible with each other. However, it is important to guarantee interoperability of the 3D-DfT architecture across the various dies in a stack, even if these dies are designed by different teams or companies; this requires standardization.…”

Section: Ieee Std P1838's Flexible Parallel Port and Its Specificatiomentioning

confidence: 99%

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

Liu

Shao

Jiao

et al. 2018

2018 IEEE 23rd European Test Symposium (ETS)

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IEEE Std P1838 is the DfT standard-under-development for 3D test access into dies meant to be used in 3D multi-die stack assemblies. P1838 is the first DfT standard to include a flexible parallel port (FPP): an optional, scalable multi-bit ('parallel') test access mechanism, offering higher test access bandwidth compared to the mandatory one-bit ('serial') port. In this paper, we describe P1838's FPP and propose a formal FPP specification language based on Google's Protocol Buffers (PBs), that potentially could become part of the standard. For a realistic example FPP, we provide its formal specification. Finally, we report on a demonstrator software tool, developed by using PBs-generated data access routines, that converts an FPP specification into a corresponding Verilog netlist. * Yu Li is currently with the ; Ming Shao is currently with Punch Powertrain, ming.shao@punchpowertrain.com; Hailong Jiao is currently also with the Shenzhen Graduate School of Peking University, jiaohl@pkusz.edu.cn. 2018 23rd IEEE European Test Symposium (ETS) !

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Section: Ieee Std P1838's Flexible Parallel Port and Its Specificatiomentioning

confidence: 99%

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

Liu

Shao

Jiao

et al. 2018

2018 IEEE 23rd European Test Symposium (ETS)

View full text Add to dashboard Cite

show abstract

“…We also need novel '3D' DfT structures that provide modular test access from (and to) the external stack I/Os to (and from) the various dies and inter-die interconnect levels, thereby transporting test stimuli and responses up and down through other dies on the way. Several ad-hoc 3D-DfT architectures have been proposed, based on IEEE Std 1149.1 [8] [9], IEEE Std 1500 [10] [11][12][13][14], and on IEEE Std 1687 [15] [16]. These architectures all have their specific strong and weak points.…”

Section: Introductionmentioning

confidence: 99%

IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs

Marinissen

McLaurin

Jiao

2016

2016 21th IEEE European Test Symposium (ETS)

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Cost-Effective TAP-Controlled Serialized Compressed Scan Architecture for 3D Stacked ICs

Cited by 2 publications

References 3 publications

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers

IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs

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