Cost-Effective Time-to-Digital Converter Using Time-Residue Feedback

A Highly Linear and Flexible FPGA-Based Time-to-Digital Converter

“…The proposed state-based TDC is compared with few other approaches in TABLE II [2], [8], [11], [17], [29], [37]. we have demonstrated our result in six separate time resolutions between 5 and 100 ps.…”

A 2.3-ps RMS Resolution Time-to-Digital Converter Implemented in a Low-Cost Cyclone V FPGA

“…In Fig. 4(b), the PSCG consists of four trains of N delay units (φ i,N > 0.5π, i ∊ [1,4]). A PLL is used to generate four clocks with 0.5π phase shifts.…”

“…HIGH-PRECISION time-to-digital converters (TDCs), which can measure short-time intervals accurately, are widely used in light detection and ranging (LiDAR), laser-ranging devices, automated test equipment (ATE), medical time-of-flight (TOF) positron emission tomography (PET) cameras, and high energy physics (HEP) experiments [1]- [5]. Many applications require TDCs with a resolution better than 10 ps that can measure the traveling distance of a photon in a vacuum with 3-mm precision [6], [7].…”

Multichannel, Low Nonlinearity Time-to-Digital Converters Based on 20 and 28 nm FPGAs

“…TDCs can be realized through analog or all-digital methods [16]. Recently, all-digital topologies have become very popular, and they can be implemented in application-specific integrated circuits (ASIC) [17], [18] or field programmable gate arrays (FPGA) [14], [19]- [34] with a subnanosecond resolution. ASIC-based TDC is a mature solution because of its better precision and linearity [35].…”