Cosyn: Hardware-software Co-synthesis Of Embedded Systems

Abstract

Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power and cost goals. In this paper, we present a co-synthesis algorithm which starts with periodic task graphs with real-time constraints and produces a lowcost heterogeneous distributed embedded system architecture meeting the constraints. The algorithm has the following features:1) it allows the use of multiple types of processing elements (PES) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network (LAN), etc.), 2) it supports both concurrent and sequential modes of communication and computation, 3) it allows both preemptive and non-preemptive scheduling, 4) it employs the concept of an association array to tackle the problem of multi-rate systems (which are commonly found in multimedia applications), 5 ) it uses a scheduler based on dynamic deadline-based priority levels for accurate performance estimation of a co-synthesis solution, 6) it uses a new task clustering technique which takes the dynamic nature of the critical path, and the existence of multiple critical paths in the task graph into account, and 7) if desired, it also optimizes the architecture for power consumption (we are not aware of any other co-synthesis algorithm that optimizes power). Application of the proposed algorithm to examples from the literature and real-life telecom transport systems shows its efficacy.

A Framework for Estimating and Minimizing Energy Dissipation of Embedded HW/SW Systems Permission to make digital/hard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commerdal advantage, the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of ACM, Inc. To copy otherwise, to republish, to post on servers or to redistribute to lists, requi

“…Previous work in core-based system design has mainly focused on performance and cost constraints. Some recent work has been presented in co-synthesis for low power [1,2]. However, the trade-off in energy dissipation among software 1 , memory and hardware has not yet been explored.…”

MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis

“…Iterative improvement algorithms start with a complete solution and make local changes to it in an attempt to improve the solution's cost [5], [12], [13]. Constructive algorithms build a system by incrementally adding components to it [14], [15]. Simulated annealing algorithms have been successfully used to partition hardware-software systems [16].…”

Hardware Implementation of Concurrent Periodic EFSMs

“…However, those existing techniques do not handle timing constraints for event execution nor guarantee real-time processing of tasks in the generated circuits. [2] has proposed a technique for guaranteeing such real-time processing. This technique supposes that multiple concurrent processes are given as the corresponding task graphs and calculates an optimal scheduling where the total cost of processors is minimized under the condition that the deadlines of all tasks are met.…”

“…The following criteria should be considered when we synthesize circuits from specifications in the proposed model: (1) guarantees for deadlock-free execution of event sequences, (2) fairness in selection of all executable branches, (3) assignment of a possibly wide time range to each I/O event execution. Therefore, the proposed synthesis technique generates circuits where all executable branches in the given specification can be selected, and only schedulable event sequences are dynamically executed depending on the execution time of the preceding events.…”