COSYN: Hardware-software co-synthesis of heterogeneous distributed embedded systems

Dave, Bharat; Lakshminarayana, G.; Jha, Niraj K.

doi:10.1109/92.748204

Cited by 111 publications

(98 citation statements)

References 14 publications

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“…One direction of these research is finding the low-power architecture by optimizing the allocation of resources and task assignment according to the power consumption (e.g. COSYN-LP [11], SLOPES [12], LOPOCOS [13]). The overview of some power aware codesign methods is presented in [4].…”

Section: Related Workmentioning

confidence: 99%

Scheduling of Distributed Algorithms for Low Power Embedded Systems

Deniziak¹,

Dzitkowski²

2016

ijacsa

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Abstract-Recently, the advent of embedded multicore processors has created interesting technologies for power management. Systems consisting of low-power and high-efficient cores create new possibilities for the optimization of power consumption. However, new design methods, dedicated to these technologies should be developed. In this paper we present a method of static task scheduling for low-power real-time embedded systems. We assume that the system is specified as a distributed algorithm, then it is implemented using multi-core embedded processor with low-power processing capabilities. We propose a new scheduling method to create the optimal or suboptimal schedule. The goal of optimization is to minimize the power consumption while all time constraints will be satisfied or the quality of service will be as high as possible. We present experimental results, obtained for sample systems, showing advantages of our method.

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Section: Related Workmentioning

confidence: 99%

Scheduling of Distributed Algorithms for Low Power Embedded Systems

Deniziak¹,

Dzitkowski²

2016

ijacsa

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“…Unfortunately, only limited research exists in reducing the energy cost of the memory system. [10] and [31] describe both a heuristic which does allocation, assignment, scheduling of multiple task-graphs. [24] and [58] compile a task-graph on a given heterogeneous architecture.…”

Section: Memory Optimization In Multi-threaded Applicationsmentioning

confidence: 99%

Power-efficient data management for dynamic applications

Marchal

Perez

Atienza

et al. 2006

System-on-Chip: Next Generation Electronics

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In recent years, the semiconductor industry has turned its focus towards heterogeneous multi-processor platforms. They are an economically viable solution for coping with the growing setup and manufacturing cost of silicon systems. Furthermore, their inherent flexibility also perfectly supports the emerging market of interactive, mobile data and content services. The platform's performance and energy depend largely on how well the data-dominated services are mapped on the memory subsystem. A crucial aspect thereby is how efficient data is transferred between the different memory layers. Several compilation techniques have been developed to optimally use the available bandwidth. Unfortunately, they do not take the interaction between multiple threads running on the different processors into account, only locally optimize the bandwidth nor deal with the dynamic behavior of these applications. The contributions of this chapter are to outline the main limitations of current techniques and to introduce an approach for dealing with the dynamic multi-threaded of our application domain. The design challenges of media-rich servicesBusiness analysts forecast a 250 billion dollar market for media-rich, mobile wireless terminals [53]. These systems require an enormous computational performance (40GOPS 1 ). Even though current PCs offer this performance requirement, they consume too much power (10-100W). Mobile devices should consume at least two or three orders of magnitude less power [30]. Furthermore, they should be cheap to successfully penetrate the consumer market. Consequently and in spite of the design issues, the engineering and manufacturing costs need to be reduced. Industry strongly believes that platforms are a potential way to meet the above challenges. The era of platform-based designA platform is a fixed micro-architecture together with a programming environment that minimizes mask-making costs and is flexible enough to work for a set of applications [4]. The production volumes can then remain high over an extended chip lifetime.Given the strong energy constraints, we must choose the flavor of these platforms. Since power is cubic to the processing frequency, parallelism is an effective to reduce power and energy consumption. Then, multiple simple processors are preferred to one complex speculative and out-of-order processor. In the right application domain, we can get better performance and spend less energy. Besides parallelism, heterogeneity is an alternative way to decrease the energy cost. For instance, the TI OMAP platform combines a RISC processor with a Digital Signal Processor (DSP). The RISC is more energy-efficient for the input/output processing and simple control-dominated 1 Giga Operations Per Second

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“…Pre-emptive and non-pre-emptive static scheduling are combined in the cosynthesis environment described in [36,37]. In many of the previous scheduling approaches researchers have assumed that processes are scheduled independently.…”

Section: Schedulability Analysismentioning

confidence: 99%