Crosstalk and delay optimization techniques for nano scale interconnects

Hasani, F.; Masoumi, Nasser

doi:10.1109/dtis.2007.4449511

Cited by 16 publications

(7 citation statements)

References 10 publications

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“…Transmission line models are more accurate than lumped models for modeling interconnect wires in deep submicron designs [4]. But as we are investigating local interconnects with wire lengths of a few micrometers, inductance effects are negligible.…”

Section: Interconnect Delay and Crosstalk Modelsmentioning

confidence: 99%

“…Coupling effects can cause interference between signals, referred to as crosstalk and may increase or decrease signal delay and as a result decrease signal integrity [2][3]. To analyze the coupling effects we need to model interconnects which require complete information of physical characteristic of the nets like the length of overlap or spacing between the nets [4]. The noise can also cause delay failure due to its effects on timing, increase power consumption due to glitches and change the logic level which cause functional failure [5][6].…”

Section: Introductionmentioning

confidence: 99%

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Interconnect sizing and spacing with consideration of buffer insertion for simultaneous crosstalk-delay optimization

Hasani

Masoumi

2008

2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era

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As integrated circuits (ICs) are scaled into nanometre dimensions and operate in gigahertz frequencies, interconnects have become critical in determining system performance and reliability. In this paper we propose a new approach to investigate crosstalk reduction techniques which helps to have simultaneous optimization of interconnect delay and crosstalk noise in deep submicron VLSI circuits. The optimization problem is modelled by solving a new cost function to find a minimum cost for both crosstalk noise and delay which are conflicting in nature. Through MATLAB software, a system of three coupled wires is modelled as a RC distributed network. The results indicate the number of optimum available solutions including wire sizing, wire spacing and buffer insertion in which crosstalk reduction techniques can be useful for both crosstalk noise and delay.

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Section: Interconnect Delay and Crosstalk Modelsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Interconnect sizing and spacing with consideration of buffer insertion for simultaneous crosstalk-delay optimization

Hasani

Masoumi

2008

2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era

Self Cite

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show abstract

“…Also, statistical alignment during assembly causes variations in field-effect regions as well as random variations from crosspoint to crosspoint in programmable diodes [14]. Due to the low controllability of the manufacturing process, the resistance of defectfree nanowires may vary as well as capacitance [15,16]. Variations in the length of nanowires cause resistive and inductive variations [16] whereas variations in nanowire width result in capacitive variations [15].…”

Section: Introductionmentioning

confidence: 98%

“…Due to the low controllability of the manufacturing process, the resistance of defectfree nanowires may vary as well as capacitance [15,16]. Variations in the length of nanowires cause resistive and inductive variations [16] whereas variations in nanowire width result in capacitive variations [15]. Crosspoints may have poor connections [8] which may result in variations of resistance.…”

Section: Introductionmentioning

confidence: 98%