Cryogenic applications of commercial electronic components

Buchanan, Ernest D.; Benford, Dominic J.; Forgione, J.; Moseley, S. H.; Wollack, Edward J.

doi:10.1016/j.cryogenics.2012.06.017

Cited by 19 publications

(4 citation statements)

References 5 publications

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“…Further analysis of the minimum differential conductance ( ( ) G T 0 ) near zero voltage for each temperature demonstrated that the principal mechanism of electric transport in the material was the charge activation of carriers. Cryogenic electronics mostly rely on materials that present temperature dependent electrical properties [44]. Therefore, the active silicon used for this study is an eligible material for cryogenics application.…”

Section: Materials and Switch Propertiesmentioning

confidence: 99%

Screen printed logic gates employing milled p-silicon as an active material

Zambou¹,

Britton²,

Härting³

2016

Flex. Print. Electron.

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This work reports on the fabrication and characterization of all screen printed logic gates. The logic gates presented in this work were printed on plain paper (80 gsm) and employed milled p-silicon as the active layer. The active material used presented a varistor-like electrical behavior in an extended range of temperatures from 340-10 K. Current driven switches were produced and used as the building blocks for the logic gates. The fundamental OR and AND boolean logic gates were demonstrated at room temperature. Their various input and output voltage levels are presented. It was also shown that the active materials and switches presented a better electrical performance at cryogenics temperature. Thus, these logic gates have the potential to be applied for use in a cryogenics environment. The advantages and limitations of the printed logic gates are discussed by comparing them to conventional logic gates.

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Section: Materials and Switch Propertiesmentioning

confidence: 99%

Screen printed logic gates employing milled p-silicon as an active material

Zambou¹,

Britton²,

Härting³

2016

Flex. Print. Electron.

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“…Although operational cryo-CMOS circuits have been demonstrated down to 30 mK [17,30,[68][69][70], unfortunately no mature models are yet available to accurately predict the behavior of passive and active devices at cryogenic temperatures [71,72]. Due to this lack of compact models at cryogenic temperatures, designers are faced to a blind-design procedure, which reduces the optimization of cryogenic integrated circuits [12,30,32,58,[73][74][75]. Using the extensive electrical characterizations of single FDSOI transistors at cryogenic temperatures, it is however possible to already design efficient circuits.…”

Section: Basic Circuit Operation At Cryogenic Temperaturesmentioning

confidence: 99%

Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS Applications

Cassé¹,

Ghibaudo²

2022

Low-Temperature Technologies and Applications

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The wide range of cryogenic applications, such as spatial, high performance computing or high-energy physics, has boosted the investigation of CMOS technology performance down to cryogenic temperatures. In particular, the readout electronics of quantum computers operating at low temperature requires larger bandwidth than spatial applications, so that advanced CMOS node has to be considered. FDSOI technology appears as a valuable solution for co-integration between qubits and consistent engineering of control and read-out. However, there is still lack of reports on literature concerning advanced CMOS nodes behavior at deep cryogenic operation, from devices electrostatics to mismatch and self-heating, all requested for the development of robust design tools. For these reasons, this chapter presents a review of electrical characterization and modeling results recently obtained on ultra-thin film FDSOI MOSFETs down to 4.2 K.

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“…Our cryogenic system has a cooling power of 0.7 W, so this heat load is negligible. CMOS components similar to the components we chose have been demonstrated to work at cryogenic temperatures 46 down to approximately 4 K; our study independently shows that CMOS devices can work at 10 K (see Section III for testing details). The peak wavelength of the light emitted by the LEDs is 655 nm (see Requirement #4 in Section II).…”

Section: Led Arraymentioning

confidence: 99%

A Scalable Cryogenic LED Module for Selectively Illuminating Kinetic Inductance Detector Arrays

Shroyer¹,

Nelson²,

Walters³

et al. 2022

Preprint

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We present the design and measured performance of an LED module for spatially mapping kinetic inductance detector arrays in the laboratory. Our novel approach uses a multiplexing (MUX) scheme that only requires seven wires to control 480 red LEDs, and the number of LEDs can be scaled up without adding any additional wires. This multiplexing approach relies on active surface mount components that can operate at cryogenic temperatures down to 10 K. Cryogenic tests in liquid nitrogen and inside our cryostat demonstrate that the MUX circuit works at 77 K and 10 K, respectively. The LED module presented here is tailored for millimeter-wave detector modules we are developing, but the approach could be broadly useful for other KID-based detector systems.

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Cryogenic applications of commercial electronic components

Cited by 19 publications

References 5 publications

Screen printed logic gates employing milled p-silicon as an active material

Screen printed logic gates employing milled p-silicon as an active material

Low Temperature Characterization and Modeling of FDSOI Transistors for Cryo CMOS Applications

A Scalable Cryogenic LED Module for Selectively Illuminating Kinetic Inductance Detector Arrays

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