Chips that contain devices with a global back-gate like the ones presented in Figs. 2 and 3 of the main text are fabricated on p + -doped Si wafers covered with 285 nm of thermal SiO 2 . The first fabrication step consists of patterning the bond pads via electron-beam lithography (EBL), W sputtering and lift-off in acetone. Afterwards, plasma-enhanced chemical vapour deposition (PECVD) of 600 nm of Si 3 N 4 is performed followed by EBL, reactive-ion etching (RIE) with CHF 3 /O 2 gases, resist lift-off and an oxygen plasma descum step to remove carbon residues. Eventually, nanowires are deposited under an optical microscope using a micromanipulator equipped with tungsten needles [S1].