Current-Mode Transceiver for Silicon Interposer Channel

Lee, Seunghun; Lee, Seon-Kyoo; Kim, Byungsub; Park, Hong-June; Sim, Jae‐Yoon

doi:10.1109/jssc.2014.2336213

Cited by 33 publications

(14 citation statements)

References 5 publications

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“…I/O energy costs range from 10 fJ/bit/mm to 180 fJ/bit/mm in on-chip links [12,20], to between 2 pJ/bit and 40 pJ/bit for typical printed circuit board (PCB) traces [8,13,14,17]. At data rates of 1 Mb/s typical of modern embedded serial links, these energy costs per bit lead to I/O power dissipation between 2 µW and 40 µW.…”

Section: Sensor Power Dissipation Is Importantmentioning

confidence: 99%

Reducing serial I/O power in error-tolerant applications by efficient lossy encoding

Rinard

Stanley-Marbell

2016

Proceedings of the 53rd Annual Design Automation Conference

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Transferring data between integrated circuits (ICs) accounts for an important fraction of the power dissipation in wearable and mobile systems. Reducing signal transitions reduces the dynamic power dissipated in the data transfer between ICs. Techniques such as Gray coding to reduce transitions between two parallel words cannot be applied when the signal transitions are between bits of a single serialized word.This paper introduces value-deviation-bounded serial encoding (VDBS encoding). VDBS encoding significantly reduces signal transitions between bits of a single serialized word, trading power efficiency for data accuracy. This tradeoff is worthwhile when the data are from signal sources such as sensors and destined for consumption by signal processing algorithms that are error-tolerant.We present analytic formulas for the Pareto-optimal VDBS encoders and introduce an efficient algorithm, Rake, that reduces transitions almost as much as the optimum transition-reducing encoder. We evaluate Rake by encoding data in a pedometer system and in a text-recognition system. For the pedometer, Rake reduces transitions by 54 % on average, in exchange for step count errors smaller than 5 %. For the text recognizer, Rake reduces transitions by 55 % on average, while maintaining OCR accuracy above 90 %.

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Section: Sensor Power Dissipation Is Importantmentioning

confidence: 99%

Reducing serial I/O power in error-tolerant applications by efficient lossy encoding

Rinard

Stanley-Marbell

2016

Proceedings of the 53rd Annual Design Automation Conference

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“…One envisioned application is short interconnects in advanced packaging such as interposers [22]. To implement such a Table 1.…”

Section: E N V I S I O N E D a P P L I C A T I O N Smentioning

confidence: 99%

Electrical performance analysis of a CPW capable of transmitting microwave and optical signals

Banan

Shokraneh

Berini³

et al. 2017

Int. J. Microw. Wireless Technol.

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A study on the microwave performance of a metallic transmission line capable of simultaneously transmitting microwave and optical signals is presented targeting millimeter-long interconnects. Conventional analytical solution is used to find the optimal structure for a given characteristic impedance. Then, functionality of the link is validated through S-parameter measurements for 3-13 mm long lines. The waveguide parameters, such as resistance, inductance, capacitance, and conductance are extracted based on a lumped circuit model. The modeling enables structure optimization for interconnect bandwidth density of 1 Gb/s/mm and more.

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“…Global interconnects are hence a bottleneck for modern day state of the art chips. Solutions to address speed and power issues for on chip interconnects are proposed which include repeater insertion, low swing circuits, current mode signaling [10][11], amplitude pre-emphasis techniques [12][13] and capacitively driven interconnects [14][15]. These techniques achieve low power and delay in signal transmission.…”

Section: Introductionmentioning

confidence: 99%

Low power driver receiver topology with delay optimization for on-chip bus interconnects

Sridhar¹,

Murty²

2018

IJET

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Demands on reducing the delay and power on integrated circuits is increasing with the development of more and more low power devices. The technology scaling and the device design manage static power dissipation. However, the dynamic power dissipation and the delays associated with the bus interconnects have to be addressed separately. A low swing driver-receiver circuit for driving and receiving the signals on the global bus interconnects is presented. Also the capacitively driven interconnects are used for the signal transmission and a series coupling capacitor is introduced at an optimized location along the bus. A substantial improvement of 55% in the delay performance is obtained with the driver-receiver and capacitively driven interconnect topology combine for the data transmission bus

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Current-Mode Transceiver for Silicon Interposer Channel

Cited by 33 publications

References 5 publications

Reducing serial I/O power in error-tolerant applications by efficient lossy encoding

Reducing serial I/O power in error-tolerant applications by efficient lossy encoding

Electrical performance analysis of a CPW capable of transmitting microwave and optical signals

Low power driver receiver topology with delay optimization for on-chip bus interconnects

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