2015
DOI: 10.1109/tcsi.2015.2495778
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Current-Reuse Transformer-Coupled Oscillators With Output Power Combining for Galvanically Isolated Power Transfer Systems

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Cited by 22 publications
(11 citation statements)
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“…Fig. 14 shows the performance of the BER as a function of channel length (10,30,90, and 120 cm) at SNR = −5 dB in both motion and stationary states. Fig.…”
Section: Results and Discussion A Bpf Test And Performance Parmentioning
confidence: 99%
See 1 more Smart Citation
“…Fig. 14 shows the performance of the BER as a function of channel length (10,30,90, and 120 cm) at SNR = −5 dB in both motion and stationary states. Fig.…”
Section: Results and Discussion A Bpf Test And Performance Parmentioning
confidence: 99%
“…Among them, mobile power supply uses battery power supply, which is absolutely independent. Using isolation transformer power supply to power the device can effectively isolate the coupling between the device and the earth ground [30]. In the experiments, the uninterrupted power supply uses the storage battery to boost the voltage to provide power for the equipment, and the energy source is the battery.…”
Section: F Experimental Protocolmentioning
confidence: 99%
“…An integrated galvanic barrier can be implemented by using silicon dioxide (SiO 2 ), which exhibits a breakdown voltage (BV) of about 1000 V/µm [3], sometimes in combination with silicon nitride (Si 3 N 4 ) and oxynitride (SiON) to further improve its isolation rating [4]. Oxide galvanic isolation has been successfully exploited in recent years for highly integrated isolated data [5][6][7] and power transfer interfaces [8][9][10][11][12] by means of on-chip capacitors or stacked transformers. However, oxide insulation can reliably provide a limited surge capability (typically 5-6 kV), since increasing the oxide thickness produces wafer mechanical stress and second order BV effects.…”
Section: Technologies For Chip-scale Galvanic Isolatorsmentioning
confidence: 99%
“…− − − 730 (1) Low/high side; (2) rms; (3) V DD = 5 V; (4) 1.3/2 GHz; (5) From micrographs in [25,26]; (6) Total area/active area; (7) Die attach film (DAF); (8) FoM 1 = (V SURGE • CMTI• f DMAX )/(t p •I DD_CH ); (9) FoM 2 = (V SURGE • CMTI)/E BIT ; (10) The best comparison is with the die-to-die isolated link reported in [25], which exploits an isolation approach based on planar coupling between side-by-side co-packaged chips, thus achieving almost the same isolation rating of our system. Among the papers in Table 3, it also reports the highest f D and the lowest E BIT , but such a performance is mainly enabled by the adopted 0.18-µm CMOS technology and consequently higher f RF with respect to our work in 0.35-µm CMOS.…”
mentioning
confidence: 99%
“…The most common oscillator topologies for galvanic isolators are the class-D [12] and the complementary cross-coupled, which are chosen according to the availability of active devices in the fabrication technology. Interesting topologies based on coupled oscillators have been reported for isolated power transfer applications to improve the performance of traditional complementary oscillators [13], [14] and for mm-wave quadcore VCOs to reduce the phase noise, while maintaining low voltage swings for reliability [15].…”
Section: Introductionmentioning
confidence: 99%