Custom Design of Multi-Level Dynamic Memory Management Subsystem for Embedded Systems

Abstract

Modern embedded systems have to run new dynamic wireless network and multimedia applications. As a result, these systems must provide run-time memory management support to allow real-time memory de/allocation, retrieving and processing of data while very limited power supply is available. Thus, its implementation must be designed to combine high speed access, low power and large data storage capacity. This is only possible by an efficient use of the memory hierarchy available in the embedded systems. In this paper, we propose a new approach to design convenient dynamic memory management subsystems making profit of the multiple memory levels. It analyzes the logical phases involved in modern dynamic applications to effectively distribute the dynamically allocated data among the multi-level memory hierarchies present in embedded devices. We assess the effectiveness of the proposed approach for three representative real-life case studies of the new dynamic application domains (i.e., network and 3D rendering applications) ported to embedded systems. The results accomplished with our approach show a very significant reduction in energy consumption (up to 40%) over state-of-theart solutions for dynamic memory management on embedded systems with typical cache-main memory architectures while respecting the real-time requirements of these applications. INTRODUCTIONOver the last few years, the main focus of the design of embedded systems has been to provide good performance and at the same time achieve low power consumption. To achieve optimal results, a good coordination between hardware and software is required. Therefore, memory-intensive applications running on embedded platforms (e.g., multimedia) must be closely linked to the underlying OS and hardware. Furthermore, new embedded applications heavily rely on dynamically allocated data due to their variable input (e.g., stream of arriving packets). This constitutes one of the most difficult design challenges when mapping them on low-power and high-speed embedded processors that are often not equipped with extensive hardware and OS support for Dynamic Memory (DM from now on) management. However, this DM management subsystem must provide efficient memory de/allocation and retrieving of the dynamically allocated data in embedded systems by combining speed, low power and large data storage. Therefore, the design and implementation of the DM management subsystem in wireless network and multimedia applications is a major design bottleneck, which requires highly customised solutions at the OS level handling the DM subsystem (i.e., DM managers) to achieve the required memory footprint, low power consumption and real-time requirements [1] . Additionally, it is common practice to develop embedded platforms with extensive use of on-chip memory subsystems (i.e., caches and scratchpads) to improve the performance of new demanding applications. However, the existing solutions for the implementation of the DM management mechanisms [2] only consider the main memory organizati...

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