Data-Centric Computing Frontiers

2020

JLPEA

Due to the amount of data involved in emerging deep learning and big data applications, operations related to data movement have quickly become a bottleneck. Data-centric computing (DCC), as enabled by processing-in-memory (PIM) and near-memory processing (NMP) paradigms, aims to accelerate these types of applications by moving the computation closer to the data. Over the past few years, researchers have proposed various memory architectures that enable DCC systems, such as logic layers in 3D-stacked memories or charge-sharing-based bitwise operations in dynamic random-access memory (DRAM). However, application-specific memory access patterns, power and thermal concerns, memory technology limitations, and inconsistent performance gains complicate the offloading of computation in DCC systems. Therefore, designing intelligent resource management techniques for computation offloading is vital for leveraging the potential offered by this new paradigm. In this article, we survey the major trends in managing PIM and NMP-based DCC systems and provide a review of the landscape of resource management techniques employed by system designers for such systems. Additionally, we discuss the future challenges and opportunities in DCC management.

Section: Prior Surveys and Scopementioning

confidence: 99%

A Survey of Resource Management for Processing-In-Memory and Near-Memory Processing Architectures

Khan

Pasricha

2020

JLPEA

“…Each model is a multi-processor-based system with sixteen processors. In addition, since we are in an era of the terabyte-sized hard disk or solid-state memory [1,17], targeted PIM-based in-memory computing systems deserve to have sufficient capacity. Thus, each model possesses 1,024 PIMs, each with a 4-GB DRAM.…”

Section: Modeling and Workloadsmentioning

confidence: 99%

“…Big data have influenced the development of high-performance computing systems that support ultra-low latency services and real-time data analytics. The trend toward big data has involved other computing paradigms such as data-centric computing, near-data processing, and processing in memory (PIM) [1]. In particular, big-data processing technologies using in-memory computing technologies have entered the spotlight.…”

Section: Introductionmentioning

confidence: 99%

Cache memory organization for processing in memory

Moon

IEICE Electron. Express

et al. 2019

A promising solution for assuring ultra-low latency in dataintensive application processing systems is processing in memory (PIM). Although most studies that have examined PIM-based computing systems have used cache memory, few have adequately explored a reasonable cache management policy for PIM. Therefore, this paper studies cache management policies for PIM-based computing systems and classifies existing PIM policies according to where they are located and how they are managed. To evaluate the policies, we model three types of PIM-based computing systems used in an in-memory system architecture. One model employs an internal-single cache, another an external cache hierarchy, and the other internal multiple cache-based PIM. We also simulate the performance and power consumption of the three models by their workloads, each with diverse characteristics. The experimental results show how cache policies influence the performance and power of PIM-based inmemory computing systems.

“…Advances in memory and integration technologies provide opportunities for profitably moving computation closer to data [12]. Some proposed architectures return to the older processor-inmemory (PIM) and "intelligent RAM" [13] ideas.…”

Section: Related Workmentioning

confidence: 99%

A microbenchmark characterization of the Emu chick

Young

Hein²,

Eswar

et al. 2019

Parallel Computing

The Emu Chick is a prototype system designed around the concept of migratory memory-side processing. Rather than transferring large amounts of data across power-hungry, high-latency interconnects, the Emu Chick moves lightweight thread contexts to near-memory cores before the beginning of each memory read. The current prototype hardware uses FPGAs to implement cache-less "Gossamer" cores for computational work and rely on a typical stationary core (PowerPC) to run basic operating system functions and migrate threads between nodes. In this multi-node characterization of the Emu Chick, we extend an earlier single-node investigation [1] of the the memory bandwidth characteristics of the system through benchmarks like STREAM, pointer chasing, and sparse matrix-vector multiplication. We compare the Emu Chick hardware to architectural simulation and an Intel Xeon-based platform. Our results demonstrate that for many basic operations the Emu Chick can use available memory bandwidth more efficiently than a more traditional, cache-based architecture although bandwidth usage suffers for computationally intensive workloads like SpMV. Moreover, the Emu Chick provides stable, predictable performance with up to 65% of the peak bandwidth utilization on a random-access pointer chasing benchmark with weak locality.