Data dependency reduction for high-performance FPGA implementation of DEFLATE compression algorithm

Kim, Young-il; Choi, Sang Woong; Jeong, Joonyong; Song, Yong Ho

doi:10.1016/j.sysarc.2019.06.005

Cited by 12 publications

(3 citation statements)

References 4 publications

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“…This is because dynamic Huffman encoding cannot begin until the dynamic Huffman tables for a block have been created, which cannot start until the entire block has finished LZ77 encoding and the frequency of symbols has been measured. This type of architecture thus also requires elastic buffering between the two encoders to hold the LZ77 encoded data until the block is finished (see [29]).…”

Section: A Compressor Resultsmentioning

confidence: 99%

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis

2020

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The Deflate compression algorithm provides one of the most widely used solutions for lossless data compression. Field-programmable gate arrays (FPGAs) are commonly used to implement hardware accelerators that speed up computation-intensive applications. In this article, FPGA-based accelerators for Deflate compression and decompression are described. These accelerators were specified in C++ and synthesized using Vivado High-Level Synthesis (HLS) for a Xilinx Virtex UltraScale+ series FPGA and a system clock frequency of 250 MHz. The proposed compressor processes data at a fixed input throughput of 4.0 GB/s and achieves a geometric mean compression ratio of 1.92 on the Calgary corpus benchmark files using static Huffman encoding. While not the first compressor synthesized using high-level synthesis, our design achieves a 25% greater throughput and an 11% greater compression ratio than the only other published design that uses Vivado HLS. The proposed decompressor design achieves average input throughputs of 196.61 MB/s and 97.40 MB/s, for statically and dynamically encoded Calgary corpus files, respectively. This is the first published decompressor design that is synthesized using high-level synthesis and provides performance that is comparable to that of the best published designs, having static throughputs 11% higher and dynamic throughputs only 10% lower than the expertly-optimized design sold by Xilinx.

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Section: A Compressor Resultsmentioning

confidence: 99%

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis

2020

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“…Being extremely computing expensive, and naturally placed in the hot-path of data communication, considerable efforts have been put on porting these software compression algorithms to hardware [20,42,72]. Microsoft [24] presented an FPGA implementation of DEFLATE where the resource utilization per compression ratio is minimized thanks to their optimized matching engine, achieving also the best public known compression throughput.…”

Section: Compression Algorithmsmentioning

confidence: 99%

Hardware acceleration of compression and encryption in SAP HANA

et al. 2022

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With the advent of cloud computing, where computational resources are expensive and data movement needs to be secured and minimized, database management systems need to reconsider their architecture to accommodate such requirements. In this paper, we present our analysis, design and evaluation of an FPGA-based hardware accelerator for offloading compression and encryption for SAP HANA, SAP's Software-as-a-Service (SaaS) in-memory database. Firstly, we identify expensive data-transformation operations in the I/O path. Then we present the design details of a system consisting of compression followed by different types of encryption to accommodate different security levels, and identify which combinations maximize performance. We also analyze the performance benefits of offloading decryption to the FPGA followed by decompression on the CPU. The experimental evaluation using SAP HANA traces shows that analytical engines can benefit from FPGA hardware offloading. The results identify a number of important trade-offs (e.g., the system can accommodate low-latency secured transactions to high-performance use cases or offer lower storage cost by also compressing payloads for less critical use cases), and provide valuable information to researchers and practitioners exploring the nascent space of hardware accelerators for database engines.

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“…We foresee our approach can be applied in a variety of applications such as checking dependencies in a task mapping scenarios [12], dependency reduction algorithms [13] and fault detection algorithms that have task execution dependencies as constraints [14].…”

Section: Related Workmentioning

confidence: 99%

Online Cycle Detection for Models with Mode-Dependent Input and Output Dependencies

Park,

Easwaran,

Borde

2021

Preprint

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In the fields of co-simulation and component-based modelling, designers import models as building blocks to create a composite model that provides more complex functionalities. Modelling tools perform instantaneous cycle detection (ICD) on the composite models having feedback loops to reject the models if the loops are mathematically unsound and to improve simulation performance. In this case, the analysis relies heavily on the availability of dependency information from the imported models. However, the cycle detection problem becomes harder when the model's input to output dependencies are mode-dependent, i.e. changes for certain events generated internally or externally as inputs. The number of possible modes created by composing such models increases significantly and unknown factors such as environmental inputs make the offline (statical) ICD a difficult task. In this paper, an online ICD method is introduced to address this issue for the models used in cyber-physical systems. The method utilises an oracle as a central source of information that can answer whether the individual models can make mode transition without creating instantaneous cycles. The oracle utilises three types of data-structures created offline that are adaptively chosen during online (runtime) depending on the frequency as well as the number of models that make mode transitions. During the analysis, the models used online are stalled from running, resulting in the discrepancy with the physical system. The objective is to detect an absence of the instantaneous cycle while minimising the stall time of the model simulation that is induced from the analysis. The benchmark results show that our method is an adequate alternative to the offline analysis methods and significantly reduces the analysis time.

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Data dependency reduction for high-performance FPGA implementation of DEFLATE compression algorithm

Cited by 12 publications

References 4 publications

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis

High-Throughput FPGA-Based Hardware Accelerators for Deflate Compression and Decompression Using High-Level Synthesis

Hardware acceleration of compression and encryption in SAP HANA

Online Cycle Detection for Models with Mode-Dependent Input and Output Dependencies

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