Data-driven self-timed RSFQ digital integrated circuit and system

Abstract-Dual-rail logic circuit elements based on rapid single-flux-quantum (RSFQ) technology have been designed and simulated.The proposed circuits can operate asynchronously, since dual-rail data include timing information in themselves. Therefore dual-rail logic scheme has a possibility of solving some problems of RSFQ circuits with flow clocking, which would become more serious as operating speed and complexity of the circuit increase.Implementation of RSFQ dual-rail AND and XOR cells is described. A scheme of transferring data from a serial flow-clocked circuit to a parallel dual-rail circuit is also proposed, which uses a fully asynchronous dual-rail demultiplexer.

Section: Data Transfer From a Flow-clocked Block To A Dual-rail Blockmentioning

confidence: 96%

“…Dual-rail logics have a possibility of solving the above problems with flow clocking [4], [5]. Dual-rail logic circuits can operate without an external timing signal since dual-rail data include timing information in themselves.…”

Section: Introductionmentioning

confidence: 99%

Rapid single-flux-quantum dual-rail logic for asynchronous circuits

Maezawa¹,

Kurosawa

Aoyagi³

et al. 1997

“…2(a)], for channels requiring timing information that the local encoding scheme cannot provide. This global encoding scheme is similar to that of dual-rail logic [3], [4], where a data signal should be sent in either a set rail or a reset rail at every event of operation.…”

Section: System-level Timing Schemementioning

confidence: 99%

A novel global self-timing methodology for BSFQ circuits

Teh

Okabe

2003

Abstract-Recently we have proposed Boolean single-fluxquantum (BSFQ) circuits, which like CMOS circuits directly support Boolean primitives, and do not require local synchronization for their elementary cells as well as for their combinational cells. However, only the cell-level timing description of the BSFQ circuits was considered, which did not specify their global timing strategy in a system-level design. In this paper, we present a novel global self-timing methodology, dual encoding hierarchical pipelining (DEHP), for the locally asynchronous BSFQ circuits. In circuit implementation, a nonvolatile memory cell named ND-DFF and a volatile memory cell named D-DFF have been designed.

“…In this research, a novel local physical timing scheme, datadriven self-timing (DDST), is developed to provide a local timing mechanism for high-speed RSFQ logic circuits based on the dual-rail coding scheme [1], [2]. This coding scheme also allows a very simple design of a novel global logical ordering protocol, vector handshaking, in which completion signaling is as simple as generating an SFQ pulse.…”

Section: Introductionmentioning

confidence: 99%

Self-timing and vector processing in RSFQ digital circuit technology

Deng

Yoshikawa

Whiteley

et al. 1999

Self Cite

As the operating speed of rapid single flux quantum (RSFQ) integrated circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, the authors present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. They also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High-speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 8-28-GHz clock generator.