Data memory organization and optimizations in application-specific systems

Panda, Preeti Ranjan; Dutt, Nikil; Nicolau, Alexandru; Catthoor, Francky; Vandecappelle, Arnout; Brockmeyer, Erik; Kulkarni, Chidamber; Greef, Eddy De

doi:10.1109/54.922803

Cited by 38 publications

(4 citation statements)

References 13 publications

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“…The use of such caches in embedded applications has been explored [35]. The combination of a scratchpad and cache has been considered [23,25]. Further, the combination of multiple caching techniques including split caches has been considered [21].…”

Section: Related Workmentioning

confidence: 99%

Superoptimization of memory subsystems

2014

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The disparity in performance between processors and main memories has led computer architects to incorporate large cache hierarchies in modern computers. Because these cache hierarchies are designed to be general-purpose, they may not provide the best possible performance for a given application. In this paper, we determine a memory subsystem well suited for a given application and main memory by discovering a memory subsystem comprised of caches, scratchpads, and other components that are combined to provide better performance. We draw motivation from the superoptimization of instruction sequences, which successfully finds unusually clever instruction sequences for programs. Targeting both ASIC and FPGA devices, we show that it is possible to discover unusual memory subsystems that provide performance improvements over a typical memory subsystem.

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Section: Related Workmentioning

confidence: 99%

Superoptimization of memory subsystems

2014

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“…For instance, a technology such as SDRAM has the ability to switch to lower power modes upon a given inactivity threshold is reached. Further approaches, applied to embedded systems, deal with memory organization and optimization [23] [2].…”

Section: Introductionmentioning

confidence: 99%

Compile-Time Silent-Store Elimination for Energy Efficiency

Bouziane

Rohou

Gamatié

2018

Proceedings of the Rapido'18 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools

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Energy-efficiency has become very critical in modern highperformance and embedded systems. In on-chip systems, memory consumes an important part of energy. Emerging non-volatile memory (NVM) technologies, such as Spin-Transfer Torque RAM (STT-RAM), offer power saving opportunities, while they suffer from high write latency.In this paper, we propose a fast evaluation of NVM integration at cache level, together with a compile-time approach for mitigating the penalty incurred by the high write latency of STT-RAM. We implement a code optimization in LLVM for reducing so-called silent stores, i.e., store instruction instances that write to memory values that were already present there. This makes our optimization portable over any architecture supporting LLVM. Then, we assess the possible benefit of such an optimization on the Rodinia benchmark suite through an analytic approach based on parameters extracted from the literature devoted to NVMs. This makes it possible to rapidly analyze the impact of NVMs on memory energy consumption. Reported results show up to 42 % energy gain when considering STT-RAM caches.

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“…The research on code transformation is orthogonal to our methodology, but it could be used as a preliminary step. 2 Solving a linear Diophantine system was proven to be of polynomial complexity, the various methods being typically based on bringing the system matrix to Hermite Normal Form [26].…”

Section: Endnotesmentioning

confidence: 99%

“…At system level, the power cost can be reduced (and, at the same time, the system performance enhanced) by introducing an optimized custom memory hierarchy [2]. Hierarchical memory organizations reduce energy consumption by assigning the frequently-accessed data to the low hierarchy levels [3], diminishing the dynamic energy consumption-which expands due to memory accesses.…”

Section: Introductionmentioning

confidence: 99%

Energy-aware memory management for embedded multidimensional signal processing applications

et al. 2016

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In real-time data-intensive multimedia processing applications, data transfer and storage significantly influence, if not dominate, all the major cost parameters of the design space-namely energy consumption, performance, and chip area. This paper presents an electronic design automation (EDA) methodology for the high-level design of hierarchical memory architectures in embedded data-intensive applications, mainly in the area of multidimensional signal processing. Different from the previous works, the problems of data assignment to the memory layers, of mapping the signals into the physical memories, and of banking the on-chip memory are addressed in a consistent way, based on the same formal model. This memory management framework employs techniques specific to the integral polyhedra based dependence analysis. The main design target is the reduction of the static and dynamic energy consumption in the hierarchical memory subsystem.

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Data memory organization and optimizations in application-specific systems

Cited by 38 publications

References 13 publications

Superoptimization of memory subsystems

Superoptimization of memory subsystems

Compile-Time Silent-Store Elimination for Energy Efficiency

Energy-aware memory management for embedded multidimensional signal processing applications

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