Data retention behavior of a SONOS type two-bit storage flash memory cell

Abstract-A V t retention distribution tail in a multitimeprogram (MTP) silicon-oxide-nitride-oxide-silicon (SONOS) memory is investigated. We characterize a single-program-chargeloss-induced ΔV t in NOR-type SONOS multilevel cells (MLCs). Our measurement shows the following: 1) A single-charge-lossinduced ΔV t exhibits an exponential distribution in magnitudes, which is attributed to a random-program-charge-induced currentpath percolation effect, and 2) the standard deviation of the exponential distribution depends on the program-charge density and increases with a program V t level in an MLC SONOS. In addition, we measure a V t retention distribution in a 512-Mb MTP SONOS memory and observe a significant V t retention tail. A numerical V t retention distribution model including the percolation effect and a Poisson-distribution-based multiple-charge-loss model is developed. Our model agrees with the measured V t retention distribution in a 512-Mb SONOS well. The observed V t tail is realized mainly due to the percolation effect.Index Terms-Model, percolation, silicon-oxide-nitride-oxidesilicon (SONOS), V t retention distribution.

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“…The log(t) dependence of V t retention loss in Fig. 3 is consistent with a Frenkel-Poole charge emission model [12].…”

supporting

confidence: 84%

$V_{t}$ Retention Distribution Tail in a Multitime-Program MLC SONOS Memory Due to a Random-Program-Charge-Induced Current-Path Percolation Effect

Chung

Huang

et al. 2012

IEEE Trans. Electron Devices

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“…The solid lines represent calculation result with h in (1) and the proportionality constant in (3) as fitting parameters. The extracted capture cross-section h of holes is about 1 . In calculation, m h m is used.…”

Section: Model Resultsmentioning

confidence: 99%

“…According to the thermionic emission model, the hole emission effect should exhibit a logarithm dependence on bake time and a linear dependence on bake temperature. The extracted hole capture cross section is about 1 . Therefore, to achieve ten years of data retention at T C, acceleration test at T C for 114 h is required.…”

Section: Discussionmentioning

confidence: 99%

“…Y UTILIZING channel hot electron injection and band-to-band hot hole injection as programming and erasing methods, respectively, injected electrons and holes will be locally trapped in a nitride layer of an "NBit" cell in a multiplex virtual ground AND (MXVAND) array [1], and two bits per cell operation is therefore achieved [2]. Since the charge storage material of Nbit cells is different from that of conventional floating gate flash devices, the understanding of data retention loss mechanisms in these nitride storage devices is critical to the improvement of the device reliability.…”

mentioning

confidence: 99%

“…Though the cells have been demonstrated to possess excellent intrinsic electron retention [3], the data retention loss caused by electron leakage via stress created oxide traps is still a reliability concern after program/erase (P/E) cycling. A g acceleration method [1] and a temperature acceleration test [4] are proposed for qualification of the NBit devices in its program state. In contrast to electrons, we observe a stronger temperature dependence of hole-lateral transport in the nitride layer in an over-erased cell [5].…”

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confidence: 99%

See 2 more Smart Citations

Lateral Migration of Trapped Holes in a Nitride Storage Flash Memory Cell and Its Qualification Methodology

Zous

Lee

Tsai

et al. 2004

IEEE Electron Device Lett.

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Abstract-The negative threshold voltage ( ) shift of a nitride storage flash memory cell in the erase state will result in an increase in leakage current. By utilizing a charge pumping method, we found that trapped hole lateral migration is responsible for this shift. Hole transport in nitride is characterized by monitoring gate induced drain leakage current and using a thermionic emission model. The hole emission induced shift shows a linear correlation with bake time in a semi-logarithm plot and its slope depends on the bake temperature. Based on the result, an accelerated qualification method for the negative drift is proposed.

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Overcoming bit loss mechanism in self‐amplified multilevel silicon‐oxide‐nitride‐oxide‐silicon memory cell

Bohara

Vishvakarma

2021

Int J Numerical Modelling

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This work reports on the triple‐level NAND flash cell realized from self‐amplified (SA) double gate (DG) tunneling‐based silicon‐oxide‐nitride‐oxide‐silicon (T‐SONOS) memory device. Through calibrated simulations, we show that capacitive coupling between the front gate and back gate can be used to store eight states (or 3 bits), that is, from “000” to “111,” in a T‐SONOS memory device with the readable difference between each level at lower programming voltages. The performance of the multilevel T‐SONOS cell is compared with the inversion mode SONOS (I‐SONOS) multilevel cell. Results highlight that gate length (Lg) scaling from 100 to 25 nm significantly deteriorates the threshold voltage associated with the lower states in the I‐SONOS multilevel cell. However, highly stable eight states can be achieved in a multi‐level T‐SONOS cell at Lg = 25 nm. The results highlight the potential of SA T‐SONOS cell for designing multilevel memory cell arrays.

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Data retention behavior of a SONOS type two-bit storage flash memory cell

Cited by 79 publications

References 8 publications

$V_{t}$ Retention Distribution Tail in a Multitime-Program MLC SONOS Memory Due to a Random-Program-Charge-Induced Current-Path Percolation Effect

$V_{t}$ Retention Distribution Tail in a Multitime-Program MLC SONOS Memory Due to a Random-Program-Charge-Induced Current-Path Percolation Effect

Lateral Migration of Trapped Holes in a Nitride Storage Flash Memory Cell and Its Qualification Methodology

Overcoming bit loss mechanism in self‐amplified multilevel silicon‐oxide‐nitride‐oxide‐silicon memory cell

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