Data-Retention Characteristics Comparison of 2D and 3D TLC NAND Flash Memories

Mizoguchi, K.; Takahashi, Tomoko; Aritome, S.; Takeuchi, Ken

doi:10.1109/imw.2017.7939077

Cited by 59 publications

(37 citation statements)

References 4 publications

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“…8 confirms that the TRE depends on the working conditions of the memory. By comparing the average fail bits count on the layer read as first and that on the rest of the block we note again that in case a) no difference is found, whereas in case b), two effects are evidenced: the TRE effects in the layer read as first and a general fail bits count increase ascribed to unavoidable V T degradation induced by retention effects [15], [16], [17]. Finally, to monitor the TRE relationship with time and temperature, we performed an additional experiment on a single physical layer consisting of a set of two consecutive reads separated by a t delay.…”

Section: Fig 4 Compares the Results Of The Test A) With Test B)mentioning

confidence: 82%

First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

Zambelli

Micheloni²,

Scommegna³

et al. 2020

IEEE J. Electron Devices Soc.

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This paper presents a new reliability threat that affects 3D-NAND Flash memories when a read operation is performed exiting from an idle state. In particular, a temporary large increase of the fail bits count is reported for the layers read as first after a sequence of program/verify and a idle retention phase. The phenomenon, hereafter called Temporary Read Errors (TRE), is not due to a permanent change of cell threshold voltage between the program verify and the following read operations, but to its transient instability occurring during the idle phase and the first read operations performed on a block. The experimental analysis has been performed on off-the-shelf gigabit-array products to characterize the dependence on the memory operating conditions. The TRE is found to be strongly dependent on the page read, on the read temperature and on the time delay between the first and the second read after the idle state. To emphasize its negative impact at system-level, we have evaluated the induced performance drop on Solid State Drives architectures. INDEX TERMS 3D-NAND flash, characterization, fail bits, read errors, reliability, solid-state drives (SSD).

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Section: Fig 4 Compares the Results Of The Test A) With Test B)mentioning

confidence: 82%

First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

Zambelli

Micheloni²,

Scommegna³

et al. 2020

IEEE J. Electron Devices Soc.

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show abstract

“…An important issue is in regard of the data retention. Indeed, 3D NAND Flash technology suffers from multiple sources of retention loss caused by temperature-activated charge loss mechanisms [23][24][25]. Either it is vertical or lateral charge loss through the structure of the memory architecture [12], the outcome is always the same: Temperature corrupts the content of the memory cells to a point where stored data are unrecoverable.…”

Section: Related Workmentioning

confidence: 99%

Mitigating Self-Heating in Solid State Drives for Industrial Internet-of-Things Edge Gateways

Zambelli

Zuolo²,

Crippa³

et al. 2020

Electronics

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Data storage in the Industrial Internet-of-Things scenario presents critical aspects related to the necessity of bringing storage devices closer to the point where data are captured. Concerns on storage temperature are to be considered especially when Solid State Drives (SSD)based on 3D NAND Flash technology are part of edge gateway architectures. Indeed, self-heating effects caused by oppressive storage demands combined with harsh environmental conditions call for proper handling at multiple abstraction levels to minimize severe performance slow downs and reliability threats. In this work, with the help of a SSD co-simulation environment that is stimulated within a realistic Industrial Internet-of-Things (IIoT) workload, we explore a methodology orthogonal to performance throttling that can be applied in synergy with the operating system of the host. Results evidenced that by leveraging on the SSD micro-architectural parameters of the queuing system it is possible to reduce the Input/Output operations Per Second (IOPS) penalty due to temperature protection mechanisms with minimum effort by the system. The methodology presented in this work opens further optimization tasks and algorithmic refinements for SSD and system designers not only in the IIoT market segment, but generally in all areas where storage power consumption is a concern.

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“…A typical example is the reliability issue generated as a result of the common CT layer in the same NAND string. In particular, lateral charge migration between adjacent cells can lead to read disturb (RD) and data retention (DR), [10][11] which issues could be much more serious with size scaling. As such, several approaches, such as metallic doping [12] and process optimization [13], were proposed to suppress charge migration in 3D CT NAND flash memory.…”

Section: Introductionmentioning

confidence: 99%

Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

Wang

et al. 2021

IEEE Access

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In charge-trap (CT) three-dimensional (3D) NAND flash memory, the transition layer between Si3N4 CT layer and SiO2 tunneling layer is inevitable, and the defects in the transition layer are expected to cause both lateral and vertical charge loss. Here, by first-principles calculations, we present a detailed study on the defects in the transition layer Si2N2O to comprehend their impacts on charge loss in CT 3D NAND flash memory. It is shown that shallow-trap centers, such as intrinsic nitrogen vacancy (VN) and interstitial Ti (Tii), can couple with the conduction band of Si2N2O to lead to lateral charge loss. On the other hand, the N substituting Si atom (NSi) and Ti substituting Si atom (TiSi) defects in the transition layer can couple through resonance with the trap centers in Si3N4, leading to vertical charge loss from the CT layer to the transition layer. Our results strongly suggest that appropriate treatment of the transition layer and hydrogen passivation are both important for avoiding charge loss in CT 3D NAND flash memory.

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Data-Retention Characteristics Comparison of 2D and 3D TLC NAND Flash Memories

Cited by 59 publications

References 4 publications

First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

First Evidence of Temporary Read Errors in TLC 3D-NAND Flash Memories Exiting From an Idle State

Mitigating Self-Heating in Solid State Drives for Industrial Internet-of-Things Edge Gateways

Charge Loss Induced by Defects of Transition Layer in Charge-Trap 3D NAND Flash Memory

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