Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators

Rubattu, Claudio; Palumbo, Francesca; Sau, Carlo; Salvador, Rubén; Sérot, Jocelyn; Desnos, Karol; Raffo, Luigi; Pelcat, Maxime

doi:10.1109/les.2018.2882989

Cited by 8 publications

(7 citation statements)

References 13 publications

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“…Dataflow DSL: Several works propose DSLs and compilers [2,5,9,13,29,38,39] to automatically synthesize dataflow circuits. Darkroom [17] compiles image-processing programs directly into linebuffered pipelines.…”

Section: Related Workmentioning

confidence: 99%

HeteroFlow

Xiang

Lai

Zhou

et al. 2022

Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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To achieve high performance with FPGA-equipped heterogeneous compute systems, it is crucial to co-optimize data placement and compute scheduling to maximize data reuse and bandwidth utilization for both on-and off-chip memory accesses. However, optimizing the data placement for FPGA accelerators is a complex task. One must acquire in-depth knowledge of the target FPGA device and its associated memory system in order to apply a set of advanced optimizations. Even with the latest high-level synthesis (HLS) tools, programmers often have to insert many low-level vendor-specific pragmas and substantially restructure the algorithmic code so that the right data are accessed at the right loop level using the right communication schemes. These code changes can significantly compromise the composability and portability of the original program.To address these challenges, we propose HeteroFlow, an FPGA accelerator programming model that decouples the algorithm specification from optimizations related to orchestrating the placement of data across a customized memory hierarchy. Specifically, we introduce a new primitive named .to(), which provides a unified programming interface for specifying data placement optimizations at different levels of granularity: (1) coarse-grained data placement between host and accelerator, (2) medium-grained kernel-level data placement within an accelerator, and (3) fine-grained data placement within a kernel. We build HeteroFlow on top of the open-source HeteroCL DSL and compilation framework. Experimental results on a set of realistic benchmarks show that, programs written in HeteroFlow can match the performance of extensively optimized manual HLS design with much fewer lines of code. CCS CONCEPTS• Hardware → Hardware description languages and compilation; High-level and register-transfer level synthesis;

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Section: Related Workmentioning

confidence: 99%

HeteroFlow

Xiang

Lai

Zhou

et al. 2022

Proceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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“…In particular, the time necessary for all the MDC steps including parsing input dataflow specifications, merging them, and generating the output files is in the order of seconds. [68]. This goal required two main actions:…”

Section: Usage Of MDC Toolmentioning

confidence: 99%

“…CAPH generates generic RTL descriptions for any kind of FPGA or even for ASIC flows. Thus, MDC has been integrated with CAPH to provide a generic fully automated CGR flow [68]. This goal required two main actions:…”

Section: Exploiting High-level Synthesismentioning

confidence: 99%

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

Fanni

Rubattu

et al. 2021

Microprocessors and Microsystems

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Modern embedded and cyber-physical systems require every day more performance, power efficiency and flexibility, to execute several profiles and functionalities targeting the ever growing adaptivity needs and preserving execution efficiency. Such requirements pushed designers towards the adoption of heterogeneous and reconfigurable substrates, which development and management is not that straightforward. Despite acceleration and flexibility are desirable in many domains, the barrier of hardware deployment and operation is still there since specific advanced expertise and skills are needed. Related challenges are effectively tackled by leveraging on automation strategies that in some cases, as in the proposed work, exploit model-based approaches. This paper is focused on the Multi-Dataflow Composer (MDC) tool, that intends to solve issues related to design, optimization and operation of coarse-grain reconfigurable hardware accelerators and their easy adoption in modern heterogeneous substrates. MDC latest features and improvements are introduced in detail and have been assessed on the so far unexplored robotics application field. A multi-profile trajectory generator for a robotic arm is implemented over a Xilinx FPGA board to show in which cases coarse-grain reconfiguration can be applied and which can be the parameters and trade-offs MDC will allow users to play with.

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“…HLS seemed to be an extremely valuable solution to tackle acceleration support, and many commercial and academical solutions proliferated over the years [12]. Nevertheless, HLS tools do not effectively support reconfiguration by construction [13]. Other solutions have also been studied to address the problem, but it has been just partially solved and widely acknowledged standard solutions are not yet there.…”

Section: Model-based Design For Reconfigurable Hw Acceleratorsmentioning

confidence: 99%

Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

et al. 2021

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With the diffusion of cyber-physical systems and internet of things, adaptivity and low power consumption became of primary importance in digital systems design. Reconfigurable heterogeneous platforms seem to be one of the most suitable choices to cope with such challenging context. However, their development and power optimization are not trivial, especially considering hardware acceleration components. On the one hand high level synthesis could simplify the design of such kind of systems, but on the other hand it can limit the positive effects of the adopted power saving techniques. In this work, the mutual impact of different high level synthesis tools and the application of the well known clock gating strategy in the development of reconfigurable accelerators is studied. The aim is to optimize a clock gating application according to the chosen high level synthesis engine and target technology (Application Specific Integrated Circuit (ASIC) or Field Programmable Gate Array (FPGA)). Different levels of application of clock gating are evaluated, including a novel multi level solution. Besides assessing the benefits and drawbacks of the clock gating application at different levels, hints for future design automation of low power reconfigurable accelerators through high level synthesis are also derived.

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Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators

Cited by 8 publications

References 13 publications

HeteroFlow

HeteroFlow

The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design

Mutual Impact between Clock Gating and High Level Synthesis in Reconfigurable Hardware Accelerators

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