DC and RF temperature behavior of deep submicron Graded Channel MOSFETs

2013 IEEE 63rd Electronic Components and Technology Conference

Bea

Murugesan

et al. 2013

A three-dimensional (3-D) LSI has many lots of throughSi vias (TSVs) and metal microbumps to achieve electrical connections between stacked thinned LSI chips, and also has organic adhesives to obtain completely bonded thinned LSI chips. However, these elements, especially microbumps and organic adhesives, induce static and dynamic local bending of the thinned LSI chips. In this study, for the first time, we investigated impacts of the static and dynamic local bending on MOSFET characteristics using a novel test structure. Introduction3-D LSI consisting of vertically stacked several thin Si chips with many TSVs and metal microbumps have attracted much attention as a promising evolution system that enhances LSI performance [1]. 3D-LSI has great advantages, such as parallel processing, high packaging density, low power consumption, short global wiring length, and high-speed operation [2]-[6]. However, it has some problems to be solved for practical applications. In particular, great interest in electrical is mechanical reliability issues are increasing among 3-D LSI researchers. Conventional 3-D LSIs consist of five key technologies, as shown in Fig. 1 [7]- [11]. TSVs and metal microbumps electrically connect between upper and lower Si chips. The thinning of the Si chips leads to a thinner LSI package and a shorter TSV. A shorter TSV makes it possible to decrease parasitic capacitance, electric resistance, and process cost. Chip alignment technology is required to have alignment accuracy less than 1 μm to realize high-density TSV interconnects. It is also necessary to fill an adhesive material called underfill among layers to increase mechanical strength. The organic adhesive surrounds metal microbumps between upper and lower thinned Si chips.

Section: Effect Of Static Local Bending Stresssupporting

confidence: 87%

Impacts of static and dynamic local bending of thinned Si chip on MOSFET performance in 3-D stacked LSI

2013 IEEE 63rd Electronic Components and Technology Conference

Bea

Murugesan

et al. 2013

“…It is well known that electron mobility increases with tensile strains and hole mobility increases with compressive stresses in the Si(100) plane. 17,18) These results agree well with theoretical predictions. In our previous study, we clarified that there were tensile strains around point A, and there were also compressive stresses around point B, as shown in Fig.…”

Section: Mosfet I-v Characteristicssupporting

confidence: 86%

Investigation of Local Bending Stress Effect on Complementary Metal–Oxide–Semiconductor Characteristics in Thinned Si Chip for Chip-to-Wafer Three-Dimensional Integration

Bea

Murugesan

et al. 2013

Jpn. J. Appl. Phys.

A three-dimensional LSI (3D-LSI) that vertically stacks Si chips with a number of through-silicon vias (TSVs) and metal microbumps has attracted much attention recently. However, there are some issues to be resolved in the fabrication of 3D-LSI. In this study, we investigated impacts of local bending stress on the performance of a complementary metal–oxide–semiconductor (CMOS) circuit fabricated in a thinned Si chip. First, we proposed a novel method and a test structure to easily induce the local bending stress in the thinned Si chip. Then, we evaluated the distribution of the local bending stress and its effects on the electrical characteristics of metal–oxide–semiconductor field-effect transistor (MOSFETs). As a result, we observed the degradations of the MOSFET currents and CMOS inverter switching behaviors in accordance with the chip local bending. Our experimental results obviously indicate that the local bending stress caused large fluctuations in the performance of the circuit fabricated in the thinned Si chip.

“…Conventional transistors are placed with the channel aligned in with the [110] crystal direction in a [001] Si wafer. 24,25) Hence, the model was set with the X-and Z-direction aligned with the [110] and [001] directions. Table I shows the physicality values of each material for simulation.…”

Section: Simulation Analysismentioning

confidence: 99%

Effect of local stress induced by thermal expansion of underfill in three-dimensional stacked IC

Hashiguchi

Tanikawa

et al. 2016

Jpn. J. Appl. Phys.

A three-dimensional stacked IC (3D IC) is a one of the promising structures for enhancing IC performances. A 3D IC consists of several materials such as a Si substrate, metal for through Si via (TSV) and microbump, organic adhesive called the underfill, and so on. These materials generate a coefficient of thermal expansion (CTE) mismatch. On the other hand, heat is generated in the Si substrate during circuit operation and in the environment outside 3D IC, for example. Both the CTE mismatch and heat generation induce local stress caused by expansion of the underfill injected around metal microbumps. In this paper, we report our investigation results of the effects of adhesive expansion on transistor performances by finite element method (FEM) simulation and measurement of transistor characteristics.