Investigation of Local Bending Stress Effect on Complementary Metal–Oxide–Semiconductor Characteristics in Thinned Si Chip for Chip-to-Wafer Three-Dimensional Integration

Abstract

A three-dimensional LSI (3D-LSI) that vertically stacks Si chips with a number of through-silicon vias (TSVs) and metal microbumps has attracted much attention recently. However, there are some issues to be resolved in the fabrication of 3D-LSI. In this study, we investigated impacts of local bending stress on the performance of a complementary metal–oxide–semiconductor (CMOS) circuit fabricated in a thinned Si chip. First, we proposed a novel method and a test structure to easily induce the local bending stress in the thinned Si chip. Then, we evaluated the distribution of the local bending stress and its effects on the electrical characteristics of metal–oxide–semiconductor field-effect transistor (MOSFETs). As a result, we observed the degradations of the MOSFET currents and CMOS inverter switching behaviors in accordance with the chip local bending. Our experimental results obviously indicate that the local bending stress caused large fluctuations in the performance of the circuit fabricated in the thinned Si chip.

Bending induced electrical response variations in ultra-thin flexible chips and device modeling

“…Some of ultra-thin CMOS inverters reported in the literature are summarized in Table VI. 186,[188][189][190][191] Only few of them have investigated the effect of bending stress on the performance. The performance of the thinned Si CMOS inverter circuit by Kino et al 191 degrades under bending stress, as shown in Fig.…”

Recent progress in 3D integration technology

“…On the other hand, we have to be careful for Cu contamination from the Cu-TSV and the backside surface in the via-middle process since the process temperature is higher than that of back-via process [23,24,25]. Mechanical stress induced by Cu-TSVs and metal microbumps, and crystal defects and crystal structure changes produced by thinning the Si substrate are also big concerns in 3D LSIs [26,27]. Both tensile and compressive stresses are induced by Cu-TSVs and metal microbumps.…”

Local Bending Stress Reduction with Room-Temperature Curing Adhesive for Decrease in Keep-out-Zone (KOZ) of 3D IC

“…As shown in Fig.1, this CTE mismatch induces local bending stress in thinned Si chips/substrates. In addition, this local bending stress would affect MOSFET performance in thinned Si chips [4]. One of the causes of this issue is temperature change due to cooling after heat curing.…”