DEC ECC design to improve memory reliability in Sub-100nm technologies

Naseer, R.; Draper, J.

doi:10.1109/icecs.2008.4674921

Cited by 64 publications

(32 citation statements)

References 10 publications

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“…Table 4 compares the number of ECC bits required for each PCM line, the latency, and the area of three ECC codes. A 128-bit segmented ECC requires 0.5ns [29]. However, the global rescue scheme introduces non-negligible latency and area overhead.…”

Section: Wt Section Sizementioning

confidence: 98%

Improving write operations in MLC phase change memory

Jiang

Zhao

Zhang

et al. 2012

IEEE International Symposium on High-Performance Comp Architecture

158

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Phase change memory (PCM) recently has emerged as a promising technology to meet the fast growing demand for large capacity memory in modern computer systems. In particular, multi-level cell (MLC) PCM that stores multiple bits in a single cell, offers high density with low per-byte fabrication cost. However, despite many advantages, such as good scalability and low leakage, PCM suffers from exceptionally slow write operations, which makes it challenging to be integrated in the memory hiearchy.In this paper, we propose architectural innovations to improve the access time of MLC PCM. Due to cell process variation, composition fluctuation and the relatively small differences among resistance levels, MLC PCM typically employs an iterative write scheme to achieve precise control, which suffers from large write access latency. To address this issue, we propose write truncation (WT) to reduce the number of write iterations with the assistance of an extra error correction code (ECC). We also propose form switch (FS) to reduce the storage overhead of the ECC. By storing highly compressible lines in SLC form, FS improves read latency as well. Our experimental results show that WT and FS improve the effective write/read latency by 57%/28% respectively, and achieve 26% performance improvement over the state of the art.

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Section: Wt Section Sizementioning

confidence: 98%

Improving write operations in MLC phase change memory

Jiang

Zhao

Zhang

et al. 2012

IEEE International Symposium on High-Performance Comp Architecture

158

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“…The EG-LDPC codes are based on the structure of Euclidean geometries over a Galois field. Among EG-LDPC codes there is a subclass of codes that is one step majority logic decodable (MLD) [12].The Figure 3 shows the memory system schematic of proposed MLDD [1].…”

Section: Detector/decodermentioning

confidence: 99%

“…Due to consequence of augmenting integration densities, there is an increase in soft errors which points the need for higher error correction capabilities [1], [3]. More advanced ECCs has been proposed for memory applications but even Double Error Correction (DEC) codes with a parallel implementation results in a significant power consumption penalty.…”

Section: Introductionmentioning

confidence: 99%

A Robust and Efficient Method For Error Detection And Correction In Memories

A¹,

Jagadeeswari²

2013

IJCA

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Due to higher integration densities, technology scaling and variation in parameters, the performance failures may occur for every application. The memory applications are also prone to single event upsets and transient errors which may lead to malfunctions. The paper deals with the idea of a novel fault detection and correction technique using EG-LDPC codes with the application mainly focused on memories. The majority logic decoding is used here, since it can correct a large number of errors. Even though the majority decoding consumes more time, it can be overcome by the proposed technique which detects the errors in less cycle time. It can obviously reduce memory access time when the data read process is error free. The use of an additional logic results in a slight area overhead in proposed method when compared to the existing technique, which is overcome by a modified implementation of majority gate. The results obtained are compared with the existing version of the technique.

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“…In the case of caches or high speed memories a parallel decoder can be an interesting option to meet the delay requirements. As an example, a parallel decoder for Double Error Correction (DEC) Bose-Chaudhuri-Hocquenghem (BCH) codes was proposed in [5]. The results show that low delay can be achieved at the cost of increased circuit area.…”

Section: Introductionmentioning

confidence: 99%